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datasheet r01ds0273ej0100 rev.1.00 page 1 of 116 oct 30, 2015 rx130 group renesas mcus features 32-bit rx cpu core ? max. operating frequency: 32 mhz capable of 50 dmips in operation at 32 mhz ? accumulator handles 64-bit results (for a single instruction) from 32-bit 32-bit operations ? multiplication and division unit handles 32-bit 32-bit operations (multiplication instructions take one cpu clock cycle) ? fast interrupt ? cisc harvard architecture with 5-stage pipeline ? variable-length instructions, ultra-compact code ? on-chip debugging circuit low power design and architecture ? operation from a single 1.8-v to 5.5-v supply ? three low power consumption modes ? low power timer (lpt) that operates during the software standby state ? supply current high-speed operating mode: 96 ?a/mhz supply current in software standby mode: 0.37 ?a ? recovery time from software standby mode: 4.8 ?s on-chip flash memory for code, no wait states ? operation at 32 mhz, read cycle of 31.25 ns ? no wait states for reading at full cpu speed ? programmable at 1.8 v ? for instructions and operands on-chip data flash memory ? 8 kbytes (1,000,000 program/erase cycles (typ.)) ? bgo (background operation) on-chip sram, no wait states ? 10- to 16-kbyte size capacities dtc ? four transfer modes ? transfer can be set for each interrupt source. elc ? module operation can be initiated by event signals without using interrupts. ? linked operation between modules is possible while the cpu is sleeping. reset and supply management ? eight types of reset, including the power-on reset (por) ? low voltage detection (lvd) with voltage settings clock functions ? external clock input frequency: up to 20 mhz ? main clock oscillator frequency: 1 to 20 mhz ? sub clock oscillator frequency: 32.768 khz ? pll circuit input: 4 mhz to 8 mhz ? low-speed on-chip oscillator: 4 mhz ? high-speed on-chip oscillator: 32 mhz 1 % ? iwdt-dedicated on-chip oscillator: 15 khz ? generate a 32.768 khz clock for the real-time clock ? on-chip clock frequency accuracy measurement circuit (cac) realtime clock ? adjustment functions (30 seconds, leap year, and error) ? calendar count mode or binary count mode selectable independent watchdog timer ? 15-khz on-chip oscillator produces a dedicated clock signal to drive iwdt operation. useful functions fo r iec60730 compliance ? self-diagnostic and disconnection-detection assistance functions for the a/d converter, clock frequency accuracy measurement circuit, independent watchdog timer, ram test assistance functions using the doc, etc. mpc ? input/output functions selectable from multiple pins up to 6 communication functions ? sci with many useful functions (up to 4 channels) asynchronous mode (fine adjustable baud rate: 0 to 255/255), clock synchronous mode, smart card interface mode ? i 2 c bus interface: transfer at up to 400 kbps, capable of smbus operation (one channel) ? rspi (one channel): transfer at up to 16 mbps up to 12 extended-function timersmpc ? 16-bit mtu: input capture, output compare, complementary pwm output, phase counting mode (six channels) ? 8-bit tmr (four channels) ? 16-bit compare-match timers (two channels) 12-bit a/d converter ? capable of conversion within 1.4 s ? 17 channels ? sampling time can be set for each channel ? conversion results compare features ? self-diagnostic function and analog input disconnection detection assistance function ? double trigger (data duplication) function for motor control d/a converter ? two channels capacitive touch sensing unit ? self-capacitance method: a single pin configures a single key, supporting up to 36 keys ? mutual capacitance method: matrix configuration with 36pins, supporting up to 324 keys comparator b ? two channels general i/o ports ? 5-v tolerant, open drain, input pull-up, switching of driving capacity temperature sensor unique id ? 32-byte id code for the mcu operating temperature range ?? 40 to +85 ? c ?? 40 to +105 ?c applications ? general industrial and consumer equipment plqp0080kb-b 12 12mm, 0.5mm pitch PLQP0064GA-A 14 14mm, 0.8mm pitch plqp0064kb-c 10 10mm, 0.5mm pitch plqp0048kb-b 7 7mm, 0.5mm pitch pwqn0048kb-a 7 7mm, 0.5mm pitch 32-mhz, 32-bit rx mcus, 50 dmip s, up to 128-kb flash memory, up to 36 pins capacitive touc h sensing unit, up to 6 comms channels, 12-bit a/d, d/a, rtc, iec60730 compliance, 1.8- v to 5.5-v single supply r01ds0273ej0100 rev.1.00 oct 30, 2015
r01ds0273ej0100 rev.1.00 page 2 of 116 oct 30, 2015 rx130 group 1. overview 1. overview 1.1 outline of specifications table 1.1 lists the specifications, and table 1.2 gives a comparison of the functions of the products in different packages. table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the p ackage type. for details, see table 1.2, comparison of functions for different packages in the rx130 group . table 1.1 outline of specifications (1/3) classification module/function description cpu cpu ? maximum operating frequency: 32 mhz ? 32-bit rx cpu ? minimum instruction execution time: one instruction per clock cycle ? address space: 4-gbyte linear ? register set general purpose: sixteen 32-bit registers control: eight 32-bit registers accumulator: one 64-bit registers ? basic instructions: 73 (variable-length instruction format) ? dsp instructions: 9 ? addressing modes: 10 ? data arrangement instructions: little endian data: selectable as little endian or big endian ? on-chip 32-bit multiplier: 32-bit 32-bit 64-bit ? on-chip divider: 32-bit 32-bit 32 bits ? barrel shifter: 32 bits memory rom ? capacity: 64 k/128 kbytes ? no-wait memory access ? programming/erasing method: serial programming (asynchronous serial communication), self-programming ram ? capacity: 10 k/16 kbytes ? no-wait memory access e2 dataflash ? capacity: 8 kbytes ? number of erase/write cycles: 1,000,000 (typ) mcu operating mode single-chip mode clock clock generation circuit ? main clock oscillator, sub-clock oscillator, low-s peed on-chip oscillator, high-speed on-chip oscillator, pll frequency synthesizer, and iwdt-dedicated on-chip oscillator ? oscillation stop detection: available ? clock frequency accuracy measurement circuit (cac) ? independent settings for the system clock (iclk), peripheral module clock (pclk), and flashif clock (fclk) the cpu and system sections such as other bus masters run in synchronization with the system clock (iclk): 32 mhz (at max.) peripheral modules run in synchronization with the pclkb: 32 mhz (at max.) the flash peripheral circuit runs in sync hronization with the fclk: 32 mhz (at max.) ? the iclk frequency can only be set to fclk, pclkb, or pclkd multiplied by n (n: 1,2,4,8,16,32,64) resets res# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset voltage detection voltage detection circuit (lvdab) ? when the voltage on vcc falls below the voltage detection level, an internal reset or internal interrupt is generated. voltage detection circuit 0 is capable of selecting the detection voltage from 4 levels voltage detection circuit 1 is capable of selecting the detection voltage from 14 levels voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels low power consumption low power consumption functions ? module stop function ? three low power consumption modes sleep mode, deep sleep mode, and software standby mode function for lower operating power consumption ? operating power control modes high-speed operating mode, middle-speed operating mode, and low-speed operating mode interrupt interrupt controller (icub) ? interrupt vectors: 101 ? external interrupts: 9 (nmi, irq0 to irq7 pins) ? non-maskable interrupts: 5 (the nmi pin, oscillation stop detection interrupt, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt, and iwdt interrupt) ? 16 levels specifiable for the order of priority
r01ds0273ej0100 rev.1.00 page 3 of 116 oct 30, 2015 rx130 group 1. overview dma data transfer controller (dtca) ? transfer modes: normal transfer, repeat transfer, and block transfer ? activation sources: interrupts ? chain transfer function i/o ports general i/o ports 80-pin /64-pin /48-pin ? i/o: 68/52/38 ? input: 1/1/1 ? pull-up resistors: 68/52/38 ? open-drain outputs: 47/35/26 ? 5-v tolerance: 4/2/2 event link controller (elc) ? event signals of 47 types can be directly connected to the module ? operations of timer modules are selectable at event input ? capable of event link operation for port b multi-function pin controller (mpc) capable of selecting the input/output function from multiple pins timers multi-function timer pulse unit 2 (mtu2a) ? (16 bits 6 channels) 1 unit ? up to 16 pulse-input/output lines and three pulse -input lines are available based on the six 16-bit timer channels ? select from among eight or seven counter-input clock signals for each channel (pclk/1, pclk/4, pclk/16, pclk/64, pclk/256, pclk/1024, mt clka, mtclkb, mtclkc, mtclkd) other than channel 5, for which only four signals are available. ? input capture function ? 21 output compare/input capture registers ? pulse output mode ? complementary pwm output mode ? reset synchronous pwm mode ? phase-counting mode ? capable of generating conversion start triggers for the a/d converter port output enable 2 (poe2a) controls the high-impedance state of the mtu?s waveform output pins compare match timer (cmt) ? (16 bits 2 channels) 1 unit ? select from among four clock signals (pclk/8, pclk/32, pclk/128, pclk/512) independent watchdog timer (iwdta) ? 14 bits 1 channel ? count clock: dedicated low-speed on-chip oscillator for the iwdt frequency divided by 1, 16, 32, 64, 128, or 256 realtime clock (rtcc) ? clock source: sub-clock ? calendar count mode or binary count mode selectable ? interrupts: alarm interrupt, periodic interrupt, and carry interrupt low power timer (lpt) ? 16 bits 1 channel ? clock source: sub-clock, dedicated low-speed on-chip oscillator for the iwdt frequency divided by 2, 4, 8, 16, or 32 8-bit timer (tmr) ? (8 bits 2 channels) 2 units ? seven internal clocks (pclk/1, pclk/2, pclk/8, pclk/32, pclk/ 64, pclk/1024, and pclk/8192) and an external clock can be selected ? pulse output and pwm output with any duty cycle are available ? two channels can be cascaded and used as a 16-bit timer communication functions serial communications interfaces (scig, scih) ? 4 channe ls (channel 1, 5, 6: scig, channel 12: scih) ? scig serial communications modes: asynchronous, clock synchronous, and smart-card interface on-chip baud rate generator allows selection of the desired bit rate choice of lsb-first or msb-first transfer average transfer rate clock can be input fr om tmr timers for sci5, sci6, and sci12 start-bit detection: level or edge detection is selectable. simple i 2 c simple spi 9-bit transfer mode bit rate modulation event linking by the elc (only on channel 5) ? scih (the following functions are added to scig) supports the serial communications protocol, whic h contains the start frame and information frame supports the lin format i 2 c bus interface (riica) ? 1 channel ? communications formats: i 2 c bus format/smbus format ? master mode or slave mode selectable ? supports fast mode table 1.1 outline of specifications (2/3) classification module/function description
r01ds0273ej0100 rev.1.00 page 4 of 116 oct 30, 2015 rx130 group 1. overview communication functions serial peripheral interface (rspia) ? 1 channel ? transfer facility using the mosi (master out, slave in), miso (master in, slave out), ssl (slave select), and rspck (rspi clock) signals enables serial transfer through spi operation (four lines) or clock-synchronous operation (three lines) ? capable of handling serial transfer as a master or slave ? data formats ? choice of lsb-first or msb-first transfer the number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or 32 bits. 128-bit buffers for transmission and reception up to four frames can be transmitted or receiv ed in a single transfer operation (with each frame having up to 32 bits) ? double buffers for both transmission and reception 12-bit a/d converter (s12ade) ? 12 bits (17 channels 1 unit) ? 12-bit resolution ? minimum conversion time: 1.4 s per channel when the adclk is operating at 32 mhz ? operating modes scan mode (single scan mode, continuous scan mode, and group scan mode) group a priority control (only for group scan mode) ? sampling variable sampling time can be set up for each channel. ? self-diagnostic function ? double trigger mode (a/d conversion data duplicated) ? detection of analog input disconnection ? conversion results compare features ? a/d conversion start conditions a software trigger, a trigger from a timer (mtu), an external trigger signal, or elc ? event linking by the elc temperature sensor (tempsa) ? 1 channel ? the voltage output from the temperature sensor is co nverted into a digital value by the 12-bit a/d converter. d/a converter (da) ? 2 channels ? 8-bit resolution ? output voltage: 0v to avcc0 crc calculator (crc) ? crc code generation for arbitrary amounts of data in 8-bit units ? select any of three generating polynomials: x 8 + x 2 + x + 1, x 16 + x 15 + x 2 + 1, or x 16 + x 12 + x 5 + 1 ? generation of crc codes for use with lsb-firs t or msb-first communications is selectable. comparator b (cmpba) ? 2 channels ? function to compare the reference voltage and the analog input voltage ? window comparator operation or standard comparator operation is selectable capacitive touch sensing unit (ctsua) detection pin: 36 channels data operation circuit (doc) comparison, addition, and subtraction of 16-bit data unique id 32-byte id code for the mcu power supply voltages/operating frequencies vcc = 1.8 to 2.4 v: 8 mhz, vcc = 2.4 to 2.7 v: 16 mhz, vcc = 2.7 to 5.5 v: 32 mhz supply current 3.1ma@32mhz operating temperature range d version: ? 40 to +85c, g version: ? 40 to +105c packages 80-pin lfqfp (plqp0080kb-b) 12 12 mm, 0.5 mm pitch 64-pin lfqfp (plqp0064kb-c) 10 10 mm, 0.5 mm pitch 64-pin lqfp (PLQP0064GA-A) 14 14 mm, 0.8 mm pitch 48-pin lfqfp (plqp0048kb-b) 7 7 mm, 0.5 mm pitch 48-pin hwqfn (pwqn0048kb-a) 7 7 mm, 0.5 mm pitch on-chip debugging system e1 emulator (fine interface) table 1.1 outline of specifications (3/3) classification module/function description
r01ds0273ej0100 rev.1.00 page 5 of 116 oct 30, 2015 rx130 group 1. overview table 1.2 comparison of functions for different packages in the rx130 group module/functions rx130 group 80 pins 64 pins 48 pins interrupts external interrupts nmi, irq0 to irq7 nmi, irq0 to irq2, irq4 to irq7 nmi, irq0, irq1, irq4 to irq7 dma data transfer controller available timers multi-function timer pulse unit 2 6 channels (mtu0 to mtu5) port output enable 2 poe0# to poe3#, poe8# 8-bit timer 2 channels 2 units compare match timer 2 channels 1 unit low power timer 1 channel realtime clock available not supported independent watchdog timer available communication functions serial communications interfaces (scig) 3 channels (sci1, 5, 6) serial communications interfaces (scih) 1 channel (sci12) i 2 c bus interface 1 channel serial peripheral interface 1 channel capacitive touch sensing unit 36 channels 32 channels 24 channels 12-bit a/d converter 17 channels 14 channels 10 channels temperature sensor available d/a converter 2 channels not supported crc calculator available event link controller available comparator b 2 channels packages 80-pin lfqfp (0.5mm) 64-pin lqfp (0.8mm) 64-pin lfqfp (0.5mm) 48-pin lfqfp (0.5mm) 48-pin hwqfn (0.5mm)
r01ds0273ej0100 rev.1.00 page 6 of 116 oct 30, 2015 rx130 group 1. overview 1.2 list of products table 1.3 is a lists of products, and figure 1.1 shows how to read the product part no., memory capacity, and package type. table 1.3 list of products group part no. orderable part no. package rom capacity ram capacity e2 dataflash maximum operating frequency operating temperature rx130 r5f51305adfn r5f51305adfn#30 plqp0080kb-b 128 kbytes 16 kbytes 8 kbytes 32 mhz ? 40 to 85c r5f51305adfm r5f51305adfm#30 plqp0064kb-c r5f51305adfk r5f51305adfk#30 PLQP0064GA-A r5f51305adfl r5f51305adfl#30 plqp0048kb-b r5f51305adne r5f51305adne#u0 pwqn0048kb-a r5f51303adfn r5f51303adfn#30 plqp0080kb-b 64 kbytes 10 kbytes r5f51303adfm r5f51303adfm#30 plqp0064kb-c r5f51303adfk r5f51303adfk#30 PLQP0064GA-A r5f51303adfl r5f51303adfl#30 plqp0048kb-b r5f51303adne r5f51303adne#u0 pwqn0048kb-a r5f51305agfn r5f51305agfn#30 plqp0080kb-b 128 kbytes 16 kbytes ? 40 to 105c r5f51305agfm r5f51305agfm#30 plqp0064kb-c r5f51305agfk r5f51305agfk#30 PLQP0064GA-A r5f51305agfl r5f51305agfl#30 plqp0048kb-b r5f51305agne r5f51305agne#u0 pwqn0048kb-a r5f51303agfn r5f51303agfn#30 plqp0080kb-b 64 kbytes 10 kbytes r5f51303agfm r5f51303agfm#30 plqp0064kb-c r5f51303agfk r5f51303agfk#30 PLQP0064GA-A r5f51303agfl r5f51303agfl#30 plqp0048kb-b r5f51303agne r5f51303agne#u0 pwqn0048kb-a
r01ds0273ej0100 rev.1.00 page 7 of 116 oct 30, 2015 rx130 group 1. overview figure 1.1 how to read the product part number package type, number of pins, and pin pitch fn: lfqfp/80/0.50 fm: lfqfp/64/0.50 fk: lqfp/64/0.80 fl: lfqfp/48/0.50 ne: hwqfn/48/0.50 d: operating ambient temperature (?40c to +85c) g: operating ambient temperature (?40c to +105c) rom, ram, and e2 dataflash capacity 5: 128 kbytes/16 kbytes/8 kbytes 3: 64 kbytes/10 kbytes/8 kbytes group name 30: rx130 group series name rx100 series type of memory f: flash memory version renesas mcu renesas semiconductor product r 5 f 5 1 d f m a503
r01ds0273ej0100 rev.1.00 page 8 of 116 oct 30, 2015 rx130 group 1. overview 1.3 block diagram figure 1.2 shows a block diagram. figure 1.2 block diagram clock generation circuit rx cpu ram rom port 1 port 2 port 4 port 5 8-bit d/a converter 2 channels crc doc e2 dataflash rtcc riica 1 channel 12-bit a/d converter 17 channels tmr 2 channels (unit 1) elc dtca icub cac iwdta port a port b port c port d mtu2a 6 channels scih 1 channel port 3 temperature sensor port e port h port j comparator b poe2a tmr 2 channels (unit 0) scig 3 channels cmt 2 channels (unit 0) rspia 1 channel operand bus instruction bus port 0 ctsua internal main bus 1 internal main bus 2 lpt internal peripheral buses 1 to 6 icub: interrupt controller dtca: data transfer controller iwdta: independent watchdog timer elc: event link controller crc: crc (cyclic redundanc y check) calculator scig/scih: serial communications interface rspia: serial peripheral interface riica: i 2 c bus interface mtu2a: multi-function timer pulse unit 2 poe2a: port output enable 2 cmt: compare match timer rtcc: realtime clock doc: data operation circuit cac: clock frequency accuracy measurement circuit ctsua: capacitive touch sensing unit tmr: 8-bit timer lpt: low power timer
r01ds0273ej0100 rev.1.00 page 9 of 116 oct 30, 2015 rx130 group 1. overview 1.4 pin functions table 1.4 lists the pin functions. table 1.4 pin functions (1/3) classifications pin name i/o description power supply vcc input power supply pin. connect it to the system power supply. vcl ? connect this pin to the vss pin via the 4.7 f smoothing capacitor used to stabilize the internal power supply. pl ace the capacitor close to the pin. vss input ground pin. connect it to the system power supply (0 v). clock xtal output pins for connecting a crystal. an external clock can be input through the extal pin. extal input xcin input input/output pins for the sub-clock oscillator. connec t a crystal between xcin and xcout. xcout output clkout output clock output pin. operating mode control md input pin for setting the operating mode. the signal levels on this pin must not be changed during operation. system control res# input reset pin. this mcu enter s the reset state when this signal goes low. cac cacref input input pin for the clock fr equency accuracy m easurement circuit. on-chip emulator fined i/o fine interface pin. interrupts nmi input non-maskable interrupt request pin. irq0 to irq7 input interrupt request pins. multi-function timer pulse unit 2 mtioc0a, mtioc0b mtioc0c, mtioc0d i/o the tgra0 to tgrd0 input capture input/output compare output/pwm output pins. mtioc1a, mtioc1b i/o the tgra1 and tgrb1 input capture input/output compare output/pwm output pins. mtioc2a, mtioc2b i/o the tgra2 and tgrb2 input capture input/output compare output/pwm output pins. mtioc3a, mtioc3b mtioc3c, mtioc3d i/o the tgra3 to tgrd3 input capture input/output compare output/pwm output pins. mtioc4a, mtioc4b mtioc4c, mtioc4d i/o the tgra4 to tgrd4 input capture input/output compare output/pwm output pins. mtic5u, mtic5v, mtic5w input the tgru5, tgrv5, and tgrw5 input capture input/external pulse input pins. mtclka, mtclkb, mtclkc, mtclkd input input pins for the external clock. port output enable 2 poe0# to poe3#, poe8# input input pins for request signals to place the mtu pins in the high impedance state. realtime clock rtcout output output pin for the 1-hz/64-hz clock. 8-bit timer tmo0 to tmo3 output compare match output pins. tmci0 to tmci3 input input pins for the external clock to be input to the counter. tmri0 to tmri3 input counter reset input pins. serial communications interface (scig) ? asynchronous mode/clock synchronous mode sck1, sck5, sck6 i/o input/output pins for the clock. rxd1, rxd5, rxd6 input input pins for received data. txd1, txd5, txd6 output output pins for transmitted data. cts1#, cts5#, cts6# input input pins for contro lling the start of transmission and reception. rts1#, rts5#, rts6# output output pins for c ontrolling the start of transmission and reception. ? simple i 2 c mode sscl1, sscl5, sscl6 i/o input/output pins for the i 2 c clock. ssda1, ssda5, ssda6 i/o input/output pins for the i 2 c data.
r01ds0273ej0100 rev.1.00 page 10 of 116 oct 30, 2015 rx130 group 1. overview serial communications interface (scig) ? simple spi mode sck1, sck5, sck6 i/o input/output pins for the clock. smiso1, smiso5, smiso6 i/o input/output pins for slave transmit data. smosi1, smosi5, smosi6 i/o input/output pins for master transmit data. ss1#, ss5#, ss6# input slave-select input pins. serial communications interface (scih) ? asynchronous mode/clock synchronous mode sck12 i/o input/output pin for the clock. rxd12 input input pin for receiving data. txd12 output output pin for transmitting data. cts12# input input pin for controlling the start of transmission and reception. rts12# output output pin for controlling the start of transmission and reception. ? simple i 2 c mode sscl12 i/o input/output pin for the i 2 c clock. ssda12 i/o input/output pin for the i 2 c data. ? simple spi mode sck12 i/o input/output pin for the clock. smiso12 i/o input/output pin for slave transmit data. smosi12 i/o input/output pin for master transmit data. ss12# input slave-select input pin. ? extended serial mode rxdx12 input input pin for data reception by scif. txdx12 output output pin for data transmission by scif. siox12 i/o input/output pin for data reception or transmission by scif. i 2 c bus interface scl i/o input/output pin for i 2 c bus interface clocks. bus can be directly driven by the n-channel open drain output. sda i/o input/output pin for i 2 c bus interface data. bus can be directly driven by the n-channel open drain output. serial peripheral interface rspcka i/o input/output pin for the rspi clock. mosia i/o input/output pin for transmitting data from the rspi master. misoa i/o input/output pin for transmitting data from the rspi slave. ssla0 i/o input/output pin to select the slave for the rspi. ssla1 to ssla3 output output pins to select the slave for the rspi. 12-bit a/d converter an000 to an007, an016 to an021, an024 to an026 input input pins for the analog signals to be processed by the a/d converter. adtrg0# input input pin for the external trigger signal that start the a/d conversion. d/a converter da0, da1 output analog out put pins of the d/a converter. comparator b cmpb0, cmpb1 input input pin for the anal og signal to be processed by comparator b. cvrefb0, cvrefb1 input analog reference voltage supply pin for comparator b. cmpob0, cmpob1 output output pin for comparator b. ctsu ts0 to ts35 i/o electrostatic capacitance measurement pins (touch pins). tscap ? connect to the vss via a decoupling capacitor (10 nf) for stabilizing the internal voltage analog power supply avcc0 input analog voltage supply pin for the 12-bit a/d converter and d/a converter. connect this pin to vcc when not using the 12-bit a/d converter and d/a converter. avss0 input analog ground pin for the 12-bit a/d converter and d/a converter. connect this pin to vss when not using the 12-bit a/d converter and d/a converter. table 1.4 pin functions (2/3) classifications pin name i/o description
r01ds0273ej0100 rev.1.00 page 11 of 116 oct 30, 2015 rx130 group 1. overview analog power supply vrefh0 input analog reference voltage supply pin for the 12-bit a/d converter. vrefl0 input analog reference ground pin for the 12-bit a/d converter. i/o ports p03 to p07 i/o 5-bit input/output pins. p12 to p17 i/o 6-bit input/output pins. p20, p21, p26, p27 i/o 4-bit input/output pins. p30 to p32, p34 to p32 i/o 7-bit input/output pins (p35 input pin). p40 to p47 i/o 8-bit input/output pins. p54, p55 i/o 2-bit input/output pins. pa0 to pa6 i/o 7-bit input/output pins. pb0 to pb7 i/o 8-bit input/output pins. pc2 to pc7 i/o 6-bit input/output pins. pd0 to pd2 i/o 3-bit input/output pins. pe0 to pe5 i/o 6-bit input/output pins. ph0 to ph3 i/o 4-bit input/output pins. pj1, pj6, pj7 i/o 3-bit input/output pins. table 1.4 pin functions (3/3) classifications pin name i/o description
r01ds0273ej0100 rev.1.00 page 12 of 116 oct 30, 2015 rx130 group 1. overview 1.5 pin assignments figure 1.3 to figure 1.6 show the pin assignments. table 1.5 to table 1.7 show the lists of pins and pin functions. figure 1.3 pin assignments of the 80-pin lfqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 pe2 pe1 pe0 pd2 pd1 pd0 p47 p46 p45 p44 p43 p42 pj7/vrefl0 p40 pj6/vrefh0 avcc0 p07 avss0 p05 p41 pc2 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p12 p13 p15 p16 p17 p20 p21 pc3 p14 pe3 pe4 pe5 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pb0 vcc pb1 pb2 pb3 pb4 pb5 pb6/pc0 pb7/pc1 vss p06 p04 vcl pj1 md xcin xcout res# p37/xtal vss p36/extal vcc p34 p32 p31 p30 p27 p26 p03 p35 rx130 group plqp0080kb-b (80-pin lfqfp) (top view) note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (80-pin lfqfp)?.
r01ds0273ej0100 rev.1.00 page 13 of 116 oct 30, 2015 rx130 group 1. overview figure 1.4 pin assignments of the 64-pin lfqfp/lqfp 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx130 group plqp0064kb-c PLQP0064GA-A (64-pin lfqfp/lqfp) (top view) pe2 pe1 pe0 p47 p46 p45 p44 p43 p42 p41 pj7/vrefl0 p40 pj6/vrefh0 avcc0 p05 avss0 pe3 pe4 pe5 pa0 pa1 pa3 pa4 pa6 vss pb0 vcc pb1 pb3 pb5 pb6/pc0 pb7/pc1 pc2 pc3 pc4 pc5 pc6 pc7 p54 p55 ph0 ph1 ph2 ph3 p14 p15 p16 p17 p03 vcl md xcin xcout res# p37/xtal vss p36/extal vcc p35 p32 p31 p30 p27 p26 note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (64-pin lfqfp/lqfp)?.
r01ds0273ej0100 rev.1.00 page 14 of 116 oct 30, 2015 rx130 group 1. overview figure 1.5 pin assignments of the 48-pin lqfp figure 1.6 pin assignments of the 48-pin hwqfn 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx130 group plqp0048kb-b (48-pin lqfp) (top view) pe2 pe1 p47 p46 p45 p42 p41 pj7/vrefl0 p40 pj6/vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0/pc0 vcc pb1/pc1 pb3/pc2 pb5/pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 18 17 16 15 14 13 note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (48-pin lqfp/hwqfn)?. rx130 group pwqn0048kb-a (48-pin hwqfn) (top view) pe2 pe1 p47 p46 p45 p42 p41 pj7/vrefl0 p40 pj6/vrefh0 avcc0 avss0 pe3 pe4 pa1 pa3 pa4 pa6 vss pb0/pc0 vcc pb1/pc1 pb3/pc2 pb5/pc3 pc4 pc5 pc6 pc7 ph0 ph1 ph2 ph3 p14 p15 p16 p17 vcl md res# p37/xtal vss p36/extal vcc p35 p31 p30 p27 p26 37 48 46 45 44 43 42 41 40 39 38 47 24 13 15 16 17 18 19 20 21 22 23 14 1 12 10 9 8 7 6 5 4 3 2 11 36 25 27 28 29 30 31 32 33 34 35 26 note: it is recommended to connect an exposed die pad to vss. note: this figure indicates the power supply pins and i/o ports. for the pin configuration, see the table ?list of pins and pin functions (48-pin lqfp/hwqfn)?.
r01ds0273ej0100 rev.1.00 page 15 of 116 oct 30, 2015 rx130 group 1. overview table 1.5 list of pins and pin functions (80-pin lfqfp) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scig, scih, rspi, riic) touch sensing others 1p 0 6 * 2 2p 0 3 * 2 da0 3p 0 4 * 2 4vcl 5p j 1 m t i o c 3 a 6md fined 7xcin 8 xcout 9 res# 10 xtal p37 11 vss 12 extal p36 13 vcc 14 p35 nmi 15 p34 mtioc0a/tmci3/poe2# sck6 irq4 16 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 ts0 irq2/rtcout 17 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# ts1 irq1 18 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 ts2 irq0 19 p27 mtioc2b/tmci3 sck1 ts3 20 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 ts4 21 p21 mtioc1b/tmci0 22 p20 mtioc1a/tmri0 23 (5v tolerant) p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 24 (5v tolerant) p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/scl irq6/rtcout/ adtrg0# 25 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 ts5 irq5 26 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# ts6 irq4 27 (5v tolerant) p13 mtioc0b/tmo3 sda irq3 28 (5v tolerant) p12 tmci1 scl irq2 29 ph3 tmci0 ts7 30 ph2 tmri0 ts8 irq1 31 ph1 tmo0 ts9 irq0 32 ph0 ts10 cacref 33 p55 mtioc4d/tmo3 ts11 34 p54 mtioc4b/tmci1 ts12 35 pc7 mtioc3a/tmo2/mtclkb misoa ts13 cacref 36 pc6 mtioc3c/mtclka/tmci2 mosia ts14 37 pc5 mtioc3b/mtclkd/tmri2 rspcka ts15 38 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 tscap 39 pc3 mtioc4d txd5/smosi5/ssda5 ts16 40 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 ts17 41 pb7/ pc1* 1 mtioc3b ts18 42 pb6/ pc0* 1 mtioc3d ts19 43 pb5 mtioc2a/mtioc1b/tmri1/ poe1# ts20 44 pb4 ts21 45 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 ts22 46 pb2 cts6#/rts6#/ss6# ts23 47 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 ts24 irq4/cmpob1 48 vcc 49 pb0 mtic5w rxd6/smiso6/sscl6/rspcka ts25
r01ds0273ej0100 rev.1.00 page 16 of 116 oct 30, 2015 rx130 group 1. overview note 1. pc0 and pc1 are valid only when t he port switching function is selected. note 2. the power source of the i/o buffer for these pins is avcc0. 50 vss 51 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia ts26 52 pa5 rspcka ts27 53 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 ts28 irq5/cvrefb1 54 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 ts29 irq6/cmpb1 55 pa2 rxd5/smiso5/sscl5/ssla3 ts30 56 pa1 mtioc0b/mtclkc sck5/ssla2 ts31 57 pa0 mtioc4a ssla1 ts32 cacref 58 pe5 mtioc4c/mtioc2b irq5/an021/cmpob0 59 pe4 mtioc4d/mtioc1a ts33 an020/cmpa2/ clkout 60 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# ts34 an019/clkout 61 pe2 mtioc4a rxd12/rxdx12/smiso 12/sscl12 ts35 irq7/an018/cvrefb0 62 pe1 mtioc4c txd12/txdx12/siox12/smosi12/ ssda12 an017/cmpb0 63 pe0 sck12 an016 64 pd2 mtioc4d sck6 irq2/an026 65 pd1 mtioc4b rxd6/smiso6/sscl6 irq1/an025 66 pd0 txd6/smosi6/ssda6 irq0/an024 67 p47* 2 an007 68 p46* 2 an006 69 p45* 2 an005 70 p44* 2 an004 71 p43* 2 an003 72 p42* 2 an002 73 p41* 2 an001 74 vrefl0 pj7* 2 75 p40* 2 an000 76 vrefh0 pj6* 2 77 avcc0 78 p07* 2 adtrg0# 79 avss0 80 p05* 2 da1 table 1.5 list of pins and pin functions (80-pin lfqfp) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scig, scih, rspi, riic) touch sensing others
r01ds0273ej0100 rev.1.00 page 17 of 116 oct 30, 2015 rx130 group 1. overview table 1.6 list of pins and pin functions (64-pin lfqfp/lqfp) (1/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scig, scih, rspi, riic) touch sensing others 1p 0 3 * 2 da0 2vcl 3md fined 4xcin 5 xcout 6 res# 7xtal p37 8 vss 9 extal p36 10 vcc 11 p35 nmi 12 p32 mtioc0c/tmo3 txd6/smosi6/ssda6 ts0 irq2/rtcout 13 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# ts1 irq1 14 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 ts2 irq0 15 p27 mtioc2b/tmci3 sck1 ts3 16 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 ts4 17 (5v tolerant) p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 18 (5v tolerant) p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/scl irq6/rtcout/ adtrg0# 19 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 ts5 irq5 20 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# ts6 irq4 21 ph3 tmci0 ts7 22 ph2 tmri0 ts8 irq1 23 ph1 tmo0 ts9 irq0 24 ph0 ts10 cacref 25 p55 mtioc4d/tmo3 ts11 26 p54 mtioc4b/tmci1 ts12 27 pc7 mtioc3a/tmo2/mtclkb misoa ts13 cacref 28 pc6 mtioc3c/mtclka/tmci2 mosia ts14 29 pc5 mtioc3b/mtclkd/tmri2 rspcka ts15 30 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 tscap 31 pc3 mtioc4d txd5/smosi5/ssda5 ts16 32 pc2 mtioc4b rxd5/smiso5/sscl5/ssla3 ts17 33 pb7/ pc1* 1 mtioc3b ts18 34 pb6/ pc0* 1 mtioc3d ts19 35 pb5 mtioc2a/mtioc1b/tmri1/ poe1# ts20 36 pb3 mtioc0a/mtioc4a/tmo0/ poe3# sck6 ts22 37 pb1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 ts24 irq4/cmpob1 38 vcc 39 pb0 mtic5w rxd6/smiso6/sscl6/rspcka ts25 40 vss 41 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia ts26 42 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 ts28 irq5/cvrefb1 43 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 ts29 irq6/cmpb1 44 pa1 mtioc0b/mtclkc sck5/ssla2 ts31 45 pa0 mtioc4a ssla1 ts32 cacref 46 pe5 mtioc4c/mtioc2b irq5/an021/cmpob0 47 pe4 mtioc4d/mtioc1a ts33 an020/cmpa2/ clkout 48 pe3 mtioc4b/poe8# cts12#/rts12#/ss12# ts34 an019/clkout
r01ds0273ej0100 rev.1.00 page 18 of 116 oct 30, 2015 rx130 group 1. overview note 1. pc0 and pc1 are valid only when t he port switching function is selected. note 2. the power source of the i/o buffer for these pins is avcc0. 49 pe2 mtioc4a rxd12/rxdx12/smiso 12/sscl12 ts35 irq7/an018/cvrefb0 50 pe1 mtioc4c txd12/txdx12/siox12/smosi12/ ssda12 an017/cmpb0 51 pe0 sck12 an016 52 p47* 2 an007 53 p46* 2 an006 54 p45* 2 an005 55 p44* 2 an004 56 p43* 2 an003 57 p42* 2 an002 58 p41* 2 an001 59 vrefl0 pj7* 2 60 p40* 2 an000 61 vrefh0 pj6* 2 62 avcc0 63 p05* 2 da1 64 avss0 table 1.6 list of pins and pin functions (64-pin lfqfp/lqfp) (2/2) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scig, scih, rspi, riic) touch sensing others
r01ds0273ej0100 rev.1.00 page 19 of 116 oct 30, 2015 rx130 group 1. overview note 1. pc0 to pc3 are valid only when t he port switching function is selected. note 2. the power source of the i/o buffer for these pins is avcc0. table 1.7 list of pins and pin functions (48-pin lqfp/hwqfn) pin no. power supply, clock, system control i/o port timers (mtu, tmr, poe) communications (scig, scih, rspi, riic) touch sensing others 1vcl 2md fined 3 res# 4xtal p37 5 vss 6 extal p36 7vcc 8p 3 5 nmi 9 p31 mtioc4d/tmci2 cts1#/rts1#/ss1# ts1 irq1 10 p30 mtioc4b/tmri3/poe8# rxd1/smiso1/sscl1 ts2 irq0 11 p27 mtioc2b/tmci3 sck1 ts3 12 p26 mtioc2a/tmo1 txd1/smosi1/ssda1 ts4 13 (5v tolerant) p17 mtioc3a/mtioc3b/tmo1/ poe8# sck1/misoa/sda irq7 14 (5v tolerant) p16 mtioc3c/mtioc3d/tmo2 txd1/smosi1/ssda1/mosia/scl irq6/adtrg0# 15 p15 mtioc0b/mtclkb/tmci2 rxd1/smiso1/sscl1 ts5 irq5 16 p14 mtioc3a/mtclka/tmri2 cts1#/rts1#/ss1# ts6 irq4 17 ph3 tmci0 ts7 18 ph2 tmri0 ts8 irq1 19 ph1 tmo0 ts9 irq0 20 ph0 ts10 cacref 21 pc7 mtioc3a/tmo2/mtclkb misoa ts13 cacref 22 pc6 mtioc3c/mtclka/tmci2 mosia ts14 23 pc5 mtioc3b/mtclkd/tmri2 rspcka ts15 24 pc4 mtioc3d/mtclkc/tmci1/ poe0# sck5/ssla0 tscap 25 pb5/pc3* 1 mtioc2a/mtioc1b/tmri1/ poe1# ts20 26 pb3/pc2* 1 mtioc0a/mtioc4a/tmo0/ poe3# sck6 ts22 27 pb1/pc1* 1 mtioc0c/mtioc4c/tmci0 txd6/smosi6/ssda6 ts24 irq4/cmpob1 28 vcc 29 pb0/pc0* 1 mtic5w rxd6/smiso6/sscl6/rspcka ts25 30 vss 31 pa6 mtic5v/mtclkb/tmci3/ poe2# cts5#/rts5#/ss5#/mosia ts26 32 pa4 mtic5u/mtclka/tmri0 txd5/smosi5/ssda5/ssla0 ts28 irq5/cvrefb1 33 pa3 mtioc0d/mtclkd rxd5/smiso5/sscl5 ts29 irq6/cmpb1 34 pa1 mtioc0b/mtclkc sck5/ssla2 ts31 35 pe4 mtioc4d/mtioc1a ts33 an020/cmpa2/ clkout 36 pe3 mtioc4b/poe8# cts12#/rts12# ts34 an019/clkout 37 pe2 mtioc4a rxd12/rxdx12/sscl12 ts35 irq7/an018/cvrefb0 38 pe1 mtioc4c txd12/txdx12/siox12/ssda12 an017/cmpb0 39 p47* 2 an007 40 p46* 2 an006 41 p45* 2 an005 42 p42* 2 an002 43 p41* 2 an001 44 vrefl0 pj7* 2 45 p40* 2 an000 46 vrefh0 pj6* 2 47 avcc0 48 avss0
r01ds0273ej0100 rev.1.00 page 20 of 116 oct 30, 2015 rx130 group 2. cpu 2. cpu figure 2.1 shows the register set of the cpu. figure 2.1 register set of the cpu note 1. the stack pointer (sp) can be the interrupt stack pointer (isp) or user stack pointer (usp), according to the value of the u bit in the psw register. usp (user stack pointer) isp (interrupt stack pointer) intb (interrupt table register) pc (program counter) psw (processor status word) bpc (backup pc) bpsw (backup psw) fintv (fast interrupt vector register) r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 (sp) *1 general-purpose registers control registers b31 b0 b31 b0 dsp instruction register b63 b0 acc (accumulator)
r01ds0273ej0100 rev.1.00 page 21 of 116 oct 30, 2015 rx130 group 2. cpu 2.1 general-purpose r egisters (r0 to r15) this cpu has 16 general-purpose registers (r 0 to r15). r0 to r15 can be used as data registers or address registers. r0, a general-purpose register, also functions as the stack pointer (sp). the stack pointer is switched to operate as the interrupt stack pointer (isp) or user stack pointer (usp) by th e value of the stack pointer se lect bit (u) in the processor status word (psw). 2.2 control registers (1) interrupt stack pointer (i sp)/user stack pointer (usp) the stack pointer (sp) can be either of two types, the interrupt stack point er (isp) or the user stack pointer (usp). whether the stack pointer operates as the isp or usp depends on the value of the stack poi nter select bit (u) in the processor status word (psw). set the isp or usp to a multiple of 4, as this reduces the nu mbers of cycles required to execute interrupt sequences and instructions entailing stack manipulation. (2) interrupt table register (intb) the interrupt table register (intb) specifies the address where the relocatable vector table starts. (3) program counter (pc) the program counter (pc) indicates the a ddress of the instruction being executed. (4) processor status word (psw) the processor status word (psw) i ndicates the results of instruction execution or the state of the cpu. (5) backup pc (bpc) the backup pc (bpc) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the program counter (pc) are saved in the bpc register. (6) backup psw (bpsw) the backup psw (bpsw) is provided to speed up response to interrupts. after a fast interrupt has been generated, the contents of the processor status word (psw ) are saved in the bpsw. the allocation of bits in the bpsw corresponds to that in the psw. (7) fast interrupt vector register (fintv) the fast interrupt vector register (fintv) is provided to speed up response to interrupts. the fintv register specifies a bran ch destination address when a fa st interrupt has been generated. 2.3 register associated with dsp instructions (1) accumulator (acc) the accumulator (acc) is a 64-bit register used for dsp instru ctions. the accumulator is also used for the multiply and multiply-and-accumulate inst ructions; emul, emulu, mul, and rmpa, in which case the prior value in the accumulator is modified by execution of the instruction. use the mvtachi and mvtaclo instructions for wr iting to the accumulator. the mvtachi and mvtaclo instructions write data to the higher-order 32 bits (bits 63 to 32) and the lower-order 32 bits (bits 31 to 0), respectively. use the mvfachi and mvfacmi instructions for reading data from th e accumulator. the mvfachi and mvfacmi instructions read data from the higher-order 32 bits (bits 63 to 32) and the middle 32 bits (bits 47 to 16), respectively.
r01ds0273ej0100 rev.1.00 page 22 of 116 oct 30, 2015 rx130 group 3. address space 3. address space 3.1 address space this lsi has a 4-gbyte address space, consisting of the rang e of addresses from 0000 0000 h to ffff ffffh. that is, linear access to an address space of up to 4 gbytes is po ssible, and this contains bo th program and data areas. figure 3.1 shows the memory maps. figure 3.1 memory map in each operating mode reserved area* 3 reserved area* 3 reserved area* 3 on-chip rom (e2 dataflash) (8 kb) reserved area* 3 single-chip mode* 1 ram* 2 on-chip rom (program rom)* 2 peripheral i/o registers peripheral i/o registers peripheral i/o registers 0000 0000h 0000 4000h 0008 0000h 0010 0000h 0010 2000h 007f c000h 007f c500h 007f fc00h 0080 0000h fffe 0000h ffff ffffh note 1. the address space in boot mode is the sa me as the address space in single-chip mode. note 2. the capacity of rom/ram differs depending on the products. note: see table 1.3, list of products, for the product type name. note 3. reserved areas should not be accessed. rom (bytes) ram (bytes) capacity address capacity address 128 kbytes fffe 0000h to ffff ffffh 16 kbytes 0000 0000h to 0000 3fffh 64 kbytes ffff 0000h to ffff ffffh 10 kbytes 0000 0000h to 0000 27ffh
r01ds0273ej0100 rev.1.00 page 23 of 116 oct 30, 2015 rx130 group 4. i/o registers 4. i/o registers this section provides information on the on-chip i/o register addresses and bit configuration. the information is given as shown below. notes on writing to registers are also given below. (1) i/o register addresses (address order) ? registers are listed from th e lower allocation addresses. ? registers are classified acco rding to module symbols. ? numbers of cycles for access indicate numbers of cycles of the given base clock. ? among the internal i/o register area, a ddresses not listed in the list of regi sters are reserved. reserved addresses must not be accessed. do not access these addresses; ot herwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. (2) notes on writing to i/o registers when writing to an i/o register , the cpu starts executing the subsequent instru ction before completing i/o register write. this may cause the subsequent instruction to be executed befo re the post-update i/o register value is reflected on the operation. as described in the following examples, sp ecial care is required for the cases in wh ich the subsequent instruction must be executed after the post-update i/o re gister value is actually reflected. [examples of cases requiring special care] ? the subsequent instruction must be execu ted while an interrupt request is disabled with the ienj bit in iern of the icu (interrupt request en able bit) cleared to 0. ? a wait instruction is executed immediately after the preprocessing for causing a transition to the low power consumption state. in the above cases, after writing to an i/o register, wait until the write operation is completed using the following procedure and then execute the subsequent instruction. (a) write to an i/o register. (b) read the value from the i/o re gister to a general register. (c) execute the operati on using the value read. (d) execute the subsequent instruction. [instruction examples] ? byte-size i/o registers mov.l #sfr_addr, r1 mov.b #sfr_data, [r1] cmp [r1].ub, r1 ;; next process ? word-size i/o registers mov.l #sfr_addr, r1 mov.w #sfr_data, [r1] cmp [r1].w, r1 ;; next process
r01ds0273ej0100 rev.1.00 page 24 of 116 oct 30, 2015 rx130 group 4. i/o registers ? longword-size i/o registers mov.l #sfr_addr, r1 mov.l #sfr_data, [r1] cmp [r1].l, r1 ;; next process if multiple registers are written to and a subsequent instruc tion should be executed after th e write operati ons are entirely completed, only read the i/o register that was last written to and execute the operation using th e value; it is not necessary to read or execute operation for all the registers that were written to. (3) number of access cycles to i/o registers for numbers of clock cycles fo r access to i/o registers, see table 4.1, list of i/o registers (address order) . the number of access cycles to i/o regist ers is obtained by following equation. * 1 number of access cycles to i/o registers = numb er of bus cycles for internal main bus 1 + number of divided clock synchronization cycles + number of bus cycles for internal peripheral buses 1 to 3, and 6 the number of bus cycles of internal peripheral buses 1 to 3, and 6 differs according to the register to be accessed. when the registers for peripheral functions connected to internal peripheral buses 2, 3, and 6 (except for bus error related registers) are accessed, the nu mber of divided clock synchr onization cycles is added. the number of divided clock synchronization cycles differs depending on the frequency ratio between iclk and pclk (or fclk) or bus access timing. in the peripheral function unit, when the fr equency ratio of iclk is equal to or gr eater than that of pclk (or fclk), the sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will be one cycle of pclk (or fclk) at a maximum. therefore, one pclk (or fclk) has been added to the number of access cycles shown in table 4.1 . when the frequency ratio of iclk is lower than that of pclk (or fclk), the subsequent bus access is started from the iclk cycle following the completion of the access to the peripheral functions. th erefore, the access cycles are described on an iclk basis. note 1. this applies to the number of cycles when the access fr om the cpu does not conflict with the instruction fetching to the external memory or bus access from the different bus master (dtc). (4) restrictions in relation to rmpa and string-manipulation instructions the allocation of data to be handled by rmpa or string-man ipulation instructions to i/o registers is prohibited, and operation is not guaranteed if this restriction is not observed. (5) notes on sleep mode and mode transitions during sleep mode or mode transitions, do not write to the sy stem control related registers (indicated by 'system' in the module symbol column in table 4.1, list of i/o registers (address order) ).
r01ds0273ej0100 rev.1.00 page 25 of 116 oct 30, 2015 rx130 group 4. i/o registers 4.1 i/o register addresses (address order) table 4.1 list of i/o register s (address order) (1 / 16) address module symbol register name register symbol number of bits access size number of access cycles 0008 0000h system mode monitor register mdmonr 16 16 3 iclk 0008 0008h system system control register 1 syscr1 16 16 3 iclk 0008 000ch system standby control register sbycr 16 16 3 iclk 0008 0010h system module stop control register a mstpcra 32 32 3 iclk 0008 0014h system module stop control register b mstpcrb 32 32 3 iclk 0008 0018h system module stop control register c mstpcrc 32 32 3 iclk 0008 001ch system module stop control register d mstpcrd 32 32 3 iclk 0008 0020h system system clock control register sckcr 32 32 3 iclk 0008 0026h system system clock control register 3 sckcr3 16 16 3 iclk 0008 0028h system pll control register pllcr 16 16 3 iclk 0008 002ah system pll control register 2 pllcr2 8 8 3 iclk 0008 0032h system main clock oscillator control register mosccr 8 8 3 iclk 0008 0033h system sub-clock oscillator control register sosccr 8 8 3 iclk 0008 0034h system low-speed on-chip osc illator control register lococr 8 8 3 iclk 0008 0035h system iwdt-dedicated on-chip oscillator control register ilococr 8 8 3 iclk 0008 0036h system high-speed on-chip oscillator control register hococr 8 8 3 iclk 0008 003ch system oscillation stabilization flag register oscovfsr 8 8 3 iclk 0008 003eh system clkout output control register ckocr 16 16 3 iclk 0008 0040h system oscillation stop detection control register ostdcr 8 8 3 iclk 0008 0041h system oscillation stop detection status register ostdsr 8 8 3 iclk 0008 0060h system low-speed on-chip oscillator trimming register locotrr 8 8 3 iclk 0008 0064h system iwdt-dedicated on-chip oscillator trimming register ilocotrr 8 8 3 iclk 0008 0068h system high-speed on-chip oscillator trimming register 0 hocotrr0 8 8 3 iclk 0008 00a0h system operating power control register opccr 8 8 3 iclk 0008 00a1h system sleep mode return clock source switching register rstckcr 8 8 3 iclk 0008 00a2h system main clock oscillator wa it control register moscwtcr 8 8 3 iclk 0008 00aah system sub operating power control register sopccr 8 8 3 iclk 0008 00b0h lpt low-power timer control register 1 lptcr1 8 8 3 iclk 0008 00b1h lpt low-power timer control register 2 lptcr2 8 8 3 iclk 0008 00b2h lpt low-power timer control register 3 lptcr3 8 8 3 iclk 0008 00b4h lpt low-power timer cycle setting register lptprd 16 16 3 iclk 0008 00b8h lpt low-power timer compare register 0 lpcmr0 16 16 3 iclk 0008 00bch lpt low-power timer standby wakeup enable register lpwucr 16 16 3 iclk 0008 00c0h system reset status register 2 rstsr2 8 8 3 iclk 0008 00c2h system software reset register swrr 16 16 3 iclk 0008 00e0h system voltage monitoring 1 circuit control register 1 lvd1cr1 8 8 3 iclk 0008 00e1h system voltage monitoring 1 circuit status register lvd1sr 8 8 3 iclk 0008 00e2h system voltage monitoring 2 circuit control register 1 lvd2cr1 8 8 3 iclk 0008 00e3h system voltage monitoring 2 circuit status register lvd2sr 8 8 3 iclk 0008 03feh system protect register prcr 16 16 3 iclk 0008 1300h bsc bus error status clear register berclr 8 8 2 iclk 0008 1304h bsc bus error monitoring enable register beren 8 8 2 iclk 0008 1308h bsc bus error status register 1 bersr1 8 8 2 iclk 0008 130ah bsc bus error status register 2 bersr2 16 16 2 iclk 0008 1310h bsc bus priority control register buspri 16 16 2 iclk 0008 2400h dtc dtc control register dtccr 8 8 2 iclk 0008 2404h dtc dtc vector base register dtcvbr 32 32 2 iclk 0008 2408h dtc dtc address mode register dtcadmod 8 8 2 iclk 0008 240ch dtc dtc module start register dtcst 8 8 2 iclk 0008 240eh dtc dtc status register dtcsts 16 16 2 iclk
r01ds0273ej0100 rev.1.00 page 26 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 7010h to 0008 70ffh icu interrupt request register 016 to 255 irn 8 8 2 iclk 0008 711bh to 0008 71ffh icu dtc activation enable register 027 to 255 dtcern 8 8 2 iclk 0008 7202h to 0008 721fh icu interrupt request enable register 02 to 1f ierm 8 8 2 iclk 0008 72e0h icu software interrupt activation register swintr 8 8 2 iclk 0008 72f0h icu fast interrupt set register fir 16 16 2 iclk 0008 7300h to 0008 73ffh icu interrupt source priority register 000 to 255 iprn 8 8 2 iclk 0008 7500h to 0008 7507h icu irq control register 0 to 7 irqcri 8 8 2 iclk 0008 7510h icu irq pin digital filter enable register 0 irqflte0 8 8 2 iclk 0008 7514h icu irq pin digital filter setting register 0 irqfltc0 16 16 2 iclk 0008 7580h icu non-maskable interrupt status register nmisr 8 8 2 iclk 0008 7581h icu non-maskable interrupt enable register nmier 8 8 2 iclk 0008 7582h icu non-maskable interrupt status clear register nmiclr 8 8 2 iclk 0008 7583h icu nmi pin interrupt control register nmicr 8 8 2 iclk 0008 7590h icu nmi pin digital filter enable register nmiflte 8 8 2 iclk 0008 7594h icu nmi pin digital filter setting register nmifltc 8 8 2 iclk 0008 8000h cmt compare match timer start register 0 cmstr0 16 16 2 or 3 pclkb 0008 8002h cmt0 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 8004h cmt0 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 8006h cmt0 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8008h cmt1 compare match timer control register cmcr 16 16 2 or 3 pclkb 0008 800ah cmt1 compare match counter cmcnt 16 16 2 or 3 pclkb 0008 800ch cmt1 compare match constant register cmcor 16 16 2 or 3 pclkb 0008 8030h iwdt iwdt refresh register iwdtrr 8 8 2 or 3 pclkb 0008 8032h iwdt iwdt control register iwdtcr 16 16 2 or 3 pclkb 0008 8034h iwdt iwdt status register iwdtsr 16 16 2 or 3 pclkb 0008 8036h iwdt iwdt reset control register iwdtrcr 8 8 2 or 3 pclkb 0008 8038h iwdt iwdt count stop control register iwdtcstpr 8 8 2 or 3 pclkb 0008 80c0h da d/a data register 0 dadr0 16 16 2 or 3 pclkb 0008 80c2h da d/a data register 1 dadr1 16 16 2 or 3 pclkb 0008 80c4h da d/a control register dacr 8 8 2 or 3 pclkb 0008 80c5h da dadrm format select register dadpr 8 8 2 or 3 pclkb 0008 80c6h da d/a a/d synchronous start control register daadscr 8 8 2 or 3 pclkb 0008 8200h tmr0 timer control register tcr 8 8 2 or 3 pclkb 0008 8201h tmr1 timer control register tcr 8 8 2 or 3 pclkb 0008 8202h tmr0 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8203h tmr1 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8204h tmr0 time constant register a tcora 8 8 2 or 3 pclkb 0008 8205h tmr1 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8206h tmr0 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8207h tmr1 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8208h tmr0 timer counter tcnt 8 8 2 or 3 pclkb 0008 8209h tmr1 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 820ah tmr0 timer counter control register tccr 8 8 2 or 3 pclkb 0008 820bh tmr1 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 820ch tmr0 timer counter start register tcstr 8 8 2 or 3 pclkb 0008 8210h tmr2 timer control register tcr 8 8 2 or 3 pclkb 0008 8211h tmr3 timer control register tcr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (2 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 27 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 8212h tmr2 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8213h tmr3 timer control/status register tcsr 8 8 2 or 3 pclkb 0008 8214h tmr2 time constant register a tcora 8 8 2 or 3 pclkb 0008 8215h tmr3 time constant register a tcora 8 8* 1 2 or 3 pclkb 0008 8216h tmr2 time constant register b tcorb 8 8 2 or 3 pclkb 0008 8217h tmr3 time constant register b tcorb 8 8* 1 2 or 3 pclkb 0008 8218h tmr2 timer counter tcnt 8 8 2 or 3 pclkb 0008 8219h tmr3 timer counter tcnt 8 8* 1 2 or 3 pclkb 0008 821ah tmr2 timer counter control register tccr 8 8 2 or 3 pclkb 0008 821bh tmr3 timer counter control register tccr 8 8* 1 2 or 3 pclkb 0008 821ch tmr2 timer counter start register tcstr 8 8 2 or 3 pclkb 0008 8280h crc crc control register crccr 8 8 2 or 3 pclkb 0008 8281h crc crc data input register crcdir 8 8 2 or 3 pclkb 0008 8282h crc crc data output register crcdor 16 16 2 or 3 pclkb 0008 8300h riic0 i 2 c bus control register 1 iccr1 8 8 2 or 3 pclkb 0008 8301h riic0 i 2 c bus control register 2 iccr2 8 8 2 or 3 pclkb 0008 8302h riic0 i 2 c bus mode register 1 icmr1 8 8 2 or 3 pclkb 0008 8303h riic0 i 2 c bus mode register 2 icmr2 8 8 2 or 3 pclkb 0008 8304h riic0 i 2 c bus mode register 3 icmr3 8 8 2 or 3 pclkb 0008 8305h riic0 i 2 c bus function enable register icfer 8 8 2 or 3 pclkb 0008 8306h riic0 i 2 c bus status enable register icser 8 8 2 or 3 pclkb 0008 8307h riic0 i 2 c bus interrupt enable register icier 8 8 2 or 3 pclkb 0008 8308h riic0 i 2 c bus status register 1 icsr1 8 8 2 or 3 pclkb 0008 8309h riic0 i 2 c bus status register 2 icsr2 8 8 2 or 3 pclkb 0008 830ah riic0 slave address register l0 sarl0 8 8 2 or 3 pclkb 0008 830bh riic0 slave address register u0 saru0 8 8 2 or 3 pclkb 0008 830ch riic0 slave address register l1 sarl1 8 8 2 or 3 pclkb 0008 830dh riic0 slave address register u1 saru1 8 8 2 or 3 pclkb 0008 830eh riic0 slave address register l2 sarl2 8 8 2 or 3 pclkb 0008 830fh riic0 slave address register u2 saru2 8 8 2 or 3 pclkb 0008 8310h riic0 i 2 c bus bit rate low-level register icbrl 8 8 2 or 3 pclkb 0008 8311h riic0 i 2 c bus bit rate high-level register icbrh 8 8 2 or 3 pclkb 0008 8312h riic0 i 2 c bus transmit data register icdrt 8 8 2 or 3 pclkb 0008 8313h riic0 i 2 c bus receive data register icdrr 8 8 2 or 3 pclkb 0008 8380h rspi0 rspi control register spcr 8 8 2 or 3 pclkb 0008 8381h rspi0 rspi slave select polarity register sslp 8 8 2 or 3 pclkb 0008 8382h rspi0 rspi pin control register sppcr 8 8 2 or 3 pclkb 0008 8383h rspi0 rspi status register spsr 8 8 2 or 3 pclkb 0008 8384h rspi0 rspi data register spdr 32 16, 32 2 or 3 pclkb/2 iclk 0008 8388h rspi0 rspi sequence control register spscr 8 8 2 or 3 pclkb 0008 8389h rspi0 rspi sequence status register spssr 8 8 2 or 3 pclkb 0008 838ah rspi0 rspi bit rate register spbr 8 8 2 or 3 pclkb 0008 838bh rspi0 rspi data control register spdcr 8 8 2 or 3 pclkb 0008 838ch rspi0 rspi clock delay register spckd 8 8 2 or 3 pclkb 0008 838dh rspi0 rspi slave select negation delay register sslnd 8 8 2 or 3 pclkb 0008 838eh rspi0 rspi next-access delay register spnd 8 8 2 or 3 pclkb 0008 838fh rspi0 rspi control register 2 spcr2 8 8 2 or 3 pclkb 0008 8390h rspi0 rspi command register 0 spcmd0 16 16 2 or 3 pclkb 0008 8392h rspi0 rspi command register 1 spcmd1 16 16 2 or 3 pclkb 0008 8394h rspi0 rspi command register 2 spcmd2 16 16 2 or 3 pclkb 0008 8396h rspi0 rspi command register 3 spcmd3 16 16 2 or 3 pclkb 0008 8398h rspi0 rspi command register 4 spcmd4 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (3 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 28 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 839ah rspi0 rspi command register 5 spcmd5 16 16 2 or 3 pclkb 0008 839ch rspi0 rspi command register 6 spcmd6 16 16 2 or 3 pclkb 0008 839eh rspi0 rspi command register 7 spcmd7 16 16 2 or 3 pclkb 0008 8600h mtu3 timer control register tcr 8 8 2 or 3 pclkb 0008 8601h mtu4 timer control register tcr 8 8 2 or 3 pclkb 0008 8602h mtu3 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8603h mtu4 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8604h mtu3 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8605h mtu3 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8606h mtu4 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8607h mtu4 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8608h mtu3 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8609h mtu4 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 860ah mtu timer output master enable registers toer 8 8 2 or 3 pclkb 0008 860dh mtu timer gate control registers tgcr 8 8 2 or 3 pclkb 0008 860eh mtu timer output control register 1 tocr1 8 8 2 or 3 pclkb 0008 860fh mtu timer output control register 2 tocr2 8 8 2 or 3 pclkb 0008 8610h mtu3 timer counter tcnt 16 16 2 or 3 pclkb 0008 8612h mtu4 timer counter tcnt 16 16 2 or 3 pclkb 0008 8614h mtu timer cycle data register tcdr 16 16 2 or 3 pclkb 0008 8616h mtu timer dead time data register tddr 16 16 2 or 3 pclkb 0008 8618h mtu3 timer general register a tgra 16 16 2 or 3 pclkb 0008 861ah mtu3 timer general register b tgrb 16 16 2 or 3 pclkb 0008 861ch mtu4 timer general register a tgra 16 16 2 or 3 pclkb 0008 861eh mtu4 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8620h mtu timer subcounter tcnts 16 16 2 or 3 pclkb 0008 8622h mtu timer cycle buffer register tcbr 16 16 2 or 3 pclkb 0008 8624h mtu3 timer general register c tgrc 16 16 2 or 3 pclkb 0008 8626h mtu3 timer general register d tgrd 16 16 2 or 3 pclkb 0008 8628h mtu4 timer general register c tgrc 16 16 2 or 3 pclkb 0008 862ah mtu4 timer general register d tgrd 16 16 2 or 3 pclkb 0008 862ch mtu3 timer status register tsr 8 8 2 or 3 pclkb 0008 862dh mtu4 timer status register tsr 8 8 2 or 3 pclkb 0008 8630h mtu timer interrupt skipping set register titcr 8 8 2 or 3 pclkb 0008 8631h mtu timer interrupt skipping counter titcnt 8 8 2 or 3 pclkb 0008 8632h mtu timer buffer transfer set register tbter 8 8 2 or 3 pclkb 0008 8634h mtu timer dead time enable register tder 8 8 2 or 3 pclkb 0008 8636h mtu timer output level buffer register tolbr 8 8 2 or 3 pclkb 0008 8638h mtu3 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8639h mtu4 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8640h mtu4 timer a/d converter start request control register tadcr 16 16 2 or 3 pclkb 0008 8644h mtu4 timer a/d converter start request cycle set register a tadcora 16 16 2 or 3 pclkb 0008 8646h mtu4 timer a/d converter start request cycle set register b tadcorb 16 16 2 or 3 pclkb 0008 8648h mtu4 timer a/d converter start request cycle set buffer register a tadcobra 16 16 2 or 3 pclkb 0008 864ah mtu4 timer a/d converter start request cycle set buffer register b tadcobrb 16 16 2 or 3 pclkb 0008 8660h mtu timer waveform control register twcr 8 8, 16 2 or 3 pclkb 0008 8680h mtu timer start register tstr 8 8, 16 2 or 3 pclkb 0008 8681h mtu timer synchronous register tsyr 8 8, 16 2 or 3 pclkb 0008 8684h mtu timer read/write enable register trwer 8 8, 16 2 or 3 pclkb 0008 8690h mtu0 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8691h mtu1 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8692h mtu2 noise filter control register nfcr 8 8, 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (4 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 29 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 8693h mtu3 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8694h mtu4 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8695h mtu5 noise filter control register nfcr 8 8, 16 2 or 3 pclkb 0008 8700h mtu0 timer control register tcr 8 8 2 or 3 pclkb 0008 8701h mtu0 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8702h mtu0 timer i/o control register h tiorh 8 8 2 or 3 pclkb 0008 8703h mtu0 timer i/o control register l tiorl 8 8 2 or 3 pclkb 0008 8704h mtu0 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8705h mtu0 timer status register tsr 8 8 2 or 3 pclkb 0008 8706h mtu0 timer counter tcnt 16 16 2 or 3 pclkb 0008 8708h mtu0 timer general register a tgra 16 16 2 or 3 pclkb 0008 870ah mtu0 timer general register b tgrb 16 16 2 or 3 pclkb 0008 870ch mtu0 timer general register c tgrc 16 16 2 or 3 pclkb 0008 870eh mtu0 timer general register d tgrd 16 16 2 or 3 pclkb 0008 8720h mtu0 timer general register e tgre 16 16 2 or 3 pclkb 0008 8722h mtu0 timer general register f tgrf 16 16 2 or 3 pclkb 0008 8724h mtu0 timer interrupt enable register 2 tier2 8 8 2 or 3 pclkb 0008 8726h mtu0 timer buffer operation transfer mode register tbtm 8 8 2 or 3 pclkb 0008 8780h mtu1 timer control register tcr 8 8 2 or 3 pclkb 0008 8781h mtu1 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8782h mtu1 timer i/o control register tior 8 8 2 or 3 pclkb 0008 8784h mtu1 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8785h mtu1 timer status register tsr 8 8 2 or 3 pclkb 0008 8786h mtu1 timer counter tcnt 16 16 2 or 3 pclkb 0008 8788h mtu1 timer general register a tgra 16 16 2 or 3 pclkb 0008 878ah mtu1 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8790h mtu1 timer input capture control register ticcr 8 8 2 or 3 pclkb 0008 8800h mtu2 timer control register tcr 8 8 2 or 3 pclkb 0008 8801h mtu2 timer mode register tmdr 8 8 2 or 3 pclkb 0008 8802h mtu2 timer i/o control register tior 8 8 2 or 3 pclkb 0008 8804h mtu2 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 8805h mtu2 timer status register tsr 8 8 2 or 3 pclkb 0008 8806h mtu2 timer counter tcnt 16 16 2 or 3 pclkb 0008 8808h mtu2 timer general register a tgra 16 16 2 or 3 pclkb 0008 880ah mtu2 timer general register b tgrb 16 16 2 or 3 pclkb 0008 8880h mtu5 timer counter u tcntu 16 16 2 or 3 pclkb 0008 8882h mtu5 timer general register u tgru 16 16 2 or 3 pclkb 0008 8884h mtu5 timer control register u tcru 8 8 2 or 3 pclkb 0008 8886h mtu5 timer i/o control register u tioru 8 8 2 or 3 pclkb 0008 8890h mtu5 timer counter v tcntv 16 16 2 or 3 pclkb 0008 8892h mtu5 timer general register v tgrv 16 16 2 or 3 pclkb 0008 8894h mtu5 timer control register v tcrv 8 8 2 or 3 pclkb 0008 8896h mtu5 timer i/o control register v tiorv 8 8 2 or 3 pclkb 0008 88a0h mtu5 timer counter w tcntw 16 16 2 or 3 pclkb 0008 88a2h mtu5 timer general register w tgrw 16 16 2 or 3 pclkb 0008 88a4h mtu5 timer control register w tcrw 8 8 2 or 3 pclkb 0008 88a6h mtu5 timer i/o control register w tiorw 8 8 2 or 3 pclkb 0008 88b2h mtu5 timer interrupt enable register tier 8 8 2 or 3 pclkb 0008 88b4h mtu5 timer start register tstr 8 8 2 or 3 pclkb 0008 88b6h mtu5 timer compare match clear register tcntcmpcl r 8 8 2 or 3 pclkb 0008 8900h poe input level control/status register 1 icsr1 16 8, 16 2 or 3 pclkb 0008 8902h poe output level control/status register 1 ocsr1 16 8, 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (5 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 30 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 8908h poe input level control/status register 2 icsr2 16 8, 16 2 or 3 pclkb 0008 890ah poe software port output enable register spoer 8 8 2 or 3 pclkb 0008 890bh poe port output enable control register 1 poecr1 8 8 2 or 3 pclkb 0008 890ch poe port output enable control register 2 poecr2 8 8 2 or 3 pclkb 0008 890eh poe input level control/status register 3 icsr3 16 8, 16 2 or 3 pclkb 0008 9000h s12ad a/d control register adcsr 16 16 2 or 3 pclkb 0008 9004h s12ad a/d channel select register a0 adansa0 16 16 2 or 3 pclkb 0008 9006h s12ad a/d channel select register a1 adansa1 16 16 2 or 3 pclkb 0008 9008h s12ad a/d-converted value addition/average function select register 0 adads0 16 16 2 or 3 pclkb 0008 900ah s12ad a/d-converted value addition/average function select register 1 adads1 16 16 2 or 3 pclkb 0008 900ch s12ad a/d-converted value addition/average count select register adadc 8 8 2 or 3 pclkb 0008 900eh s12ad a/d control extended register adcer 16 16 2 or 3 pclkb 0008 9010h s12ad a/d conversion start trigger select register adstrgr 16 16 2 or 3 pclkb 0008 9012h s12ad a/d conversion extended input control register adexicr 16 16 2 or 3 pclkb 0008 9014h s12ad a/d channel select register b0 adansb0 16 16 2 or 3 pclkb 0008 9016h s12ad a/d channel select register b1 adansb1 16 16 2 or 3 pclkb 0008 9018h s12ad a/d data duplication register addbldr 16 16 2 or 3 pclkb 0008 901ah s12ad a/d temperature sensor data register adtsdr 16 16 2 or 3 pclkb 0008 901ch s12ad a/d internal reference voltage data register adocdr 16 16 2 or 3 pclkb 0008 901eh s12ad a/d self-diagnosis data register adrd 16 16 2 or 3 pclkb 0008 9020h s12ad a/d data register 0 addr0 16 16 2 or 3 pclkb 0008 9022h s12ad a/d data register 1 addr1 16 16 2 or 3 pclkb 0008 9024h s12ad a/d data register 2 addr2 16 16 2 or 3 pclkb 0008 9026h s12ad a/d data register 3 addr3 16 16 2 or 3 pclkb 0008 9028h s12ad a/d data register 4 addr4 16 16 2 or 3 pclkb 0008 902ah s12ad a/d data register 5 addr5 16 16 2 or 3 pclkb 0008 902ch s12ad a/d data register 6 addr6 16 16 2 or 3 pclkb 0008 902eh s12ad a/d data register 7 addr7 16 16 2 or 3 pclkb 0008 9040h s12ad a/d data register 16 addr16 16 16 2 or 3 pclkb 0008 9042h s12ad a/d data register 17 addr17 16 16 2 or 3 pclkb 0008 9044h s12ad a/d data register 18 addr18 16 16 2 or 3 pclkb 0008 9046h s12ad a/d data register 19 addr19 16 16 2 or 3 pclkb 0008 9048h s12ad a/d data register 20 addr20 16 16 2 or 3 pclkb 0008 904ah s12ad a/d data register 21 addr21 16 16 2 or 3 pclkb 0008 9050h s12ad a/d data register 24 addr24 16 16 2 or 3 pclkb 0008 9052h s12ad a/d data register 25 addr25 16 16 2 or 3 pclkb 0008 9054h s12ad a/d data register 26 addr26 16 16 2 or 3 pclkb 0008 907ah s12ad a/d disconnection detection control register addiscr 8 8 2 or 3 pclkb 0008 907dh s12ad a/d event link control register adelccr 8 8 2 or 3 pclkb 0008 9080h s12ad a/d group scan priority control register adgspcr 16 16 2 or 3 pclkb 0008 908ah s12ad a/d high-potential/low-potential reference voltage control register adhvrefcn t 8 8 2 or 3 pclkb 0008 908ch s12ad a/d compare function window a/b status monitor register adwinmon 8 8 2 or 3 pclkb 0008 9090h s12ad a/d compare function control register adcmpcr 16 16 2 or 3 pclkb 0008 9092h s12ad a/d compare function window a extended input select register adcmpanse r 8 8 2 or 3 pclkb 0008 9093h s12ad a/d compare function window a extended input comparison condition setting register adcmpler 8 8 2 or 3 pclkb 0008 9094h s12ad a/d compare function window a channel select register 0 adcmpansr 0 16 16 2 or 3 pclkb 0008 9096h s12ad a/d compare function window a channel select register 1 adcmpansr 1 16 16 2 or 3 pclkb 0008 9098h s12ad a/d compare function window a comparison condition setting register 0 adcmplr0 16 16 2 or 3 pclkb 0008 909ah s12ad a/d compare function window a comparison condition setting register 1 adcmplr1 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (6 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 31 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 909ch s12ad a/d compare function window a lower-side level setting register adcmpdr0 16 16 2 or 3 pclkb 0008 909eh s12ad a/d compare function window a upper-side level setting register adcmpdr1 16 16 2 or 3 pclkb 0008 90a0h s12ad a/d compare function window a channel status register 0 adcmpsr0 16 16 2 or 3 pclkb 0008 90a2h s12ad a/d compare function window a channel status register 1 adcmpsr1 16 16 2 or 3 pclkb 0008 90a4h s12ad a/d compare function window a extended input channel status register adcmpser 8 8 2 or 3 pclkb 0008 90a6h s12ad a/d compare function window b channel select register adcmpbnsr 8 8 2 or 3 pclkb 0008 90a8h s12ad a/d compare function window b lower-side level setting register adwinllb 16 16 2 or 3 pclkb 0008 90aah s12ad a/d compare function window b upper-side level setting register adwinulb 16 16 2 or 3 pclkb 0008 90ach s12ad a/d compare function window b status register adcmpbsr 8 8 2 or 3 pclkb 0008 90b0h s12ad a/d data storage buffer register 0 adbuf0 16 16 2 or 3 pclkb 0008 90b2h s12ad a/d data storage buffer register 1 adbuf1 16 16 2 or 3 pclkb 0008 90b4h s12ad a/d data storage buffer register 2 adbuf2 16 16 2 or 3 pclkb 0008 90b6h s12ad a/d data storage buffer register 3 adbuf3 16 16 2 or 3 pclkb 0008 90b8h s12ad a/d data storage buffer register 4 adbuf4 16 16 2 or 3 pclkb 0008 90bah s12ad a/d data storage buffer register 5 adbuf5 16 16 2 or 3 pclkb 0008 90bch s12ad a/d data storage buffer register 6 adbuf6 16 16 2 or 3 pclkb 0008 90beh s12ad a/d data storage buffer register 7 adbuf7 16 16 2 or 3 pclkb 0008 90c0h s12ad a/d data storage buffer register 8 adbuf8 16 16 2 or 3 pclkb 0008 90c2h s12ad a/d data storage buffer register 9 adbuf9 16 16 2 or 3 pclkb 0008 90c4h s12ad a/d data storage buffer register 10 adbuf10 16 16 2 or 3 pclkb 0008 90c6h s12ad a/d data storage buffer register 11 adbuf11 16 16 2 or 3 pclkb 0008 90c8h s12ad a/d data storage buffer register 12 adbuf12 16 16 2 or 3 pclkb 0008 90cah s12ad a/d data storage buffer register 13 adbuf13 16 16 2 or 3 pclkb 0008 90cch s12ad a/d data storage buffer register 14 adbuf14 16 16 2 or 3 pclkb 0008 90ceh s12ad a/d data storage buffer register 15 adbuf15 16 16 2 or 3 pclkb 0008 90d0h s12ad a/d data storage buffer enable register adbufen 8 8 2 or 3 pclkb 0008 90d2h s12ad a/d data storage buffer pointer register adbufptr 8 8 2 or 3 pclkb 0008 90ddh s12ad a/d sampling state register l adsstrl 8 8 2 or 3 pclkb 0008 90deh s12ad a/d sampling state register t adsstrt 8 8 2 or 3 pclkb 0008 90dfh s12ad a/d sampling state register o adsstro 8 8 2 or 3 pclkb 0008 90e0h s12ad a/d sampling state register 0 adsstr0 8 8 2 or 3 pclkb 0008 90e1h s12ad a/d sampling state register 1 adsstr1 8 8 2 or 3 pclkb 0008 90e2h s12ad a/d sampling state register 2 adsstr2 8 8 2 or 3 pclkb 0008 90e3h s12ad a/d sampling state register 3 adsstr3 8 8 2 or 3 pclkb 0008 90e4h s12ad a/d sampling state register 4 adsstr4 8 8 2 or 3 pclkb 0008 90e5h s12ad a/d sampling state register 5 adsstr5 8 8 2 or 3 pclkb 0008 90e6h s12ad a/d sampling state register 6 adsstr6 8 8 2 or 3 pclkb 0008 90e7h s12ad a/d sampling state register 7 adsstr7 8 8 2 or 3 pclkb 0008 a020h sci1 serial mode register smr 8 8 2 or 3 pclkb 0008 a021h sci1 bit rate register brr 8 8 2 or 3 pclkb 0008 a022h sci1 serial control register scr 8 8 2 or 3 pclkb 0008 a023h sci1 transmit data register tdr 8 8 2 or 3 pclkb 0008 a024h sci1 serial status register ssr 8 8 2 or 3 pclkb 0008 a025h sci1 receive data register rdr 8 8 2 or 3 pclkb 0008 a026h sci1 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a027h sci1 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a028h sci1 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a029h sci1 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a02ah sci1 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a02bh sci1 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a02ch sci1 i 2 c status register sisr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (7 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 32 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 a02dh sci1 spi mode register spmr 8 8 2 or 3 pclkb 0008 a02eh sci1 transmit data register hl tdrhl 16 16 2 or 3 pclkb 0008 a02eh sci1 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a02fh sci1 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a030h sci1 receive data register hl rdrhl 16 16 2 or 3 pclkb 0008 a030h sci1 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a031h sci1 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a032h sci1 modulation duty register mddr 8 8 2 or 3 pclkb 0008 a0a0h sci5 serial mode register smr 8 8 2 or 3 pclkb 0008 a0a1h sci5 bit rate register brr 8 8 2 or 3 pclkb 0008 a0a2h sci5 serial control register scr 8 8 2 or 3 pclkb 0008 a0a3h sci5 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0a4h sci5 serial status register ssr 8 8 2 or 3 pclkb 0008 a0a5h sci5 receive data register rdr 8 8 2 or 3 pclkb 0008 a0a6h sci5 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0a7h sci5 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0a8h sci5 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0a9h sci5 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0aah sci5 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0abh sci5 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0ach sci5 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0adh sci5 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0aeh sci5 transmit data register hl tdrhl 16 16 2 or 3 pclkb 0008 a0aeh sci5 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 a0afh sci5 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a0b0h sci5 receive data register hl rdrhl 16 16 2 or 3 pclkb 0008 a0b0h sci5 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a0b1h sci5 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a0b2h sci5 modulation duty register mddr 8 8 2 or 3 pclkb 0008 a0c0h sci6 serial mode register smr 8 8 2 or 3 pclkb 0008 a0c1h sci6 bit rate register brr 8 8 2 or 3 pclkb 0008 a0c2h sci6 serial control register scr 8 8 2 or 3 pclkb 0008 a0c3h sci6 transmit data register tdr 8 8 2 or 3 pclkb 0008 a0c4h sci6 serial status register ssr 8 8 2 or 3 pclkb 0008 a0c5h sci6 receive data register rdr 8 8 2 or 3 pclkb 0008 a0c6h sci6 smart card mode register scmr 8 8 2 or 3 pclkb 0008 a0c7h sci6 serial extended mode register semr 8 8 2 or 3 pclkb 0008 a0c8h sci6 noise filter setting register snfr 8 8 2 or 3 pclkb 0008 a0c9h sci6 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 a0cah sci6 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 a0cbh sci6 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 a0cch sci6 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 a0cdh sci6 spi mode register spmr 8 8 2 or 3 pclkb 0008 a0ceh sci6 transmit data register hl tdrhl 16 16 2 or 3 pclkb 0008 a0ceh sci6 transmit data register h tdrh 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (8 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 33 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 a0cfh sci6 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 a0d0h sci6 receive data register hl rdrhl 16 16 2 or 3 pclkb 0008 a0d0h sci6 receive data register h rdrh 8 8 2 or 3 pclkb 0008 a0d1h sci6 receive data register l rdrl 8 8 2 or 3 pclkb 0008 a0d2h sci6 modulation duty register mddr 8 8 2 or 3 pclkb 0008 b000h cac cac control register 0 cacr0 8 8 2 or 3 pclkb 0008 b001h cac cac control register 1 cacr1 8 8 2 or 3 pclkb 0008 b002h cac cac control register 2 cacr2 8 8 2 or 3 pclkb 0008 b003h cac cac interrupt request enable register caicr 8 8 2 or 3 pclkb 0008 b004h cac cac status register castr 8 8 2 or 3 pclkb 0008 b006h cac cac upper-limit value setting register caulvr 16 16 2 or 3 pclkb 0008 b008h cac cac lower-limit value setting register callvr 16 16 2 or 3 pclkb 0008 b00ah cac cac counter buffer register cacntbr 16 16 2 or 3 pclkb 0008 b080h doc doc control register docr 8 8 2 or 3 pclkb 0008 b082h doc doc data input register dodir 16 16 2 or 3 pclkb 0008 b084h doc doc data setting register dodsr 16 16 2 or 3 pclkb 0008 b100h elc event link control register elcr 8 8 2 or 3 pclkb 0008 b102h elc event link setting register 1 elsr1 8 8 2 or 3 pclkb 0008 b103h elc event link setting register 2 elsr2 8 8 2 or 3 pclkb 0008 b104h elc event link setting register 3 elsr3 8 8 2 or 3 pclkb 0008 b105h elc event link setting register 4 elsr4 8 8 2 or 3 pclkb 0008 b108h elc event link setting register 7 elsr7 8 8 2 or 3 pclkb 0008 b109h elc event link setting register 8 elsr8 8 8 2 or 3 pclkb 0008 b10bh elc event link setting register 10 elsr10 8 8 2 or 3 pclkb 0008 b10dh elc event link setting register 12 elsr12 8 8 2 or 3 pclkb 0008 b10fh elc event link setting register 14 elsr14 8 8 2 or 3 pclkb 0008 b110h elc event link setting register 15 elsr15 8 8 2 or 3 pclkb 0008 b111h elc event link setting register 16 elsr16 8 8 2 or 3 pclkb 0008 b113h elc event link setting register 18 elsr18 8 8 2 or 3 pclkb 0008 b115h elc event link setting register 20 elsr20 8 8 2 or 3 pclkb 0008 b117h elc event link setting register 22 elsr22 8 8 2 or 3 pclkb 0008 b119h elc event link setting register 24 elsr24 8 8 2 or 3 pclkb 0008 b11ah elc event link setting register 25 elsr25 8 8 2 or 3 pclkb 0008 b11fh elc event link option setting register a elopa 8 8 2 or 3 pclkb 0008 b120h elc event link option setting register b elopb 8 8 2 or 3 pclkb 0008 b121h elc event link option setting register c elopc 8 8 2 or 3 pclkb 0008 b122h elc event link option setting register d elopd 8 8 2 or 3 pclkb 0008 b123h elc port group setting register 1 pgr1 8 8 2 or 3 pclkb 0008 b125h elc port group control register 1 pgc1 8 8 2 or 3 pclkb 0008 b127h elc port buffer register 1 pdbf1 8 8 2 or 3 pclkb 0008 b129h elc event link port setting register 0 pel0 8 8 2 or 3 pclkb 0008 b12ah elc event link port setting register 1 pel1 8 8 2 or 3 pclkb 0008 b12dh elc event link software event generation register elsegr 8 8 2 or 3 pclkb 0008 b300h sci12 serial mode register smr 8 8 2 or 3 pclkb 0008 b301h sci12 bit rate register brr 8 8 2 or 3 pclkb 0008 b302h sci12 serial control register scr 8 8 2 or 3 pclkb 0008 b303h sci12 transmit data register tdr 8 8 2 or 3 pclkb 0008 b304h sci12 serial status register ssr 8 8 2 or 3 pclkb 0008 b305h sci12 receive data register rdr 8 8 2 or 3 pclkb 0008 b306h sci12 smart card mode register scmr 8 8 2 or 3 pclkb 0008 b307h sci12 serial extended mode register semr 8 8 2 or 3 pclkb 0008 b308h sci12 noise filter setting register snfr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (9 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 34 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 b309h sci12 i 2 c mode register 1 simr1 8 8 2 or 3 pclkb 0008 b30ah sci12 i 2 c mode register 2 simr2 8 8 2 or 3 pclkb 0008 b30bh sci12 i 2 c mode register 3 simr3 8 8 2 or 3 pclkb 0008 b30ch sci12 i 2 c status register sisr 8 8 2 or 3 pclkb 0008 b30dh sci12 spi mode register spmr 8 8 2 or 3 pclkb 0008 b30eh sci12 transmit data register hl tdrhl 16 16 2 or 3 pclkb 0008 b30eh sci12 transmit data register h tdrh 8 8 2 or 3 pclkb 0008 b30fh sci12 transmit data register l tdrl 8 8 2 or 3 pclkb 0008 b310h sci12 receive data register hl rdrhl 16 16 2 or 3 pclkb 0008 b310h sci12 receive data register h rdrh 8 8 2 or 3 pclkb 0008 b311h sci12 receive data register l rdrl 8 8 2 or 3 pclkb 0008 b312h sci12 modulation duty register mddr 8 8 2 or 3 pclkb 0008 b320h sci12 extended serial module enable register esmer 8 8 2 or 3 pclkb 0008 b321h sci12 control register 0 cr0 8 8 2 or 3 pclkb 0008 b322h sci12 control register 1 cr1 8 8 2 or 3 pclkb 0008 b323h sci12 control register 2 cr2 8 8 2 or 3 pclkb 0008 b324h sci12 control register 3 cr3 8 8 2 or 3 pclkb 0008 b325h sci12 port control register pcr 8 8 2 or 3 pclkb 0008 b326h sci12 interrupt control register icr 8 8 2 or 3 pclkb 0008 b327h sci12 status register str 8 8 2 or 3 pclkb 0008 b328h sci12 status clear register stcr 8 8 2 or 3 pclkb 0008 b329h sci12 control field 0 data register cf0dr 8 8 2 or 3 pclkb 0008 b32ah sci12 control field 0 compare enable register cf0cr 8 8 2 or 3 pclkb 0008 b32bh sci12 control field 0 receive data register cf0rr 8 8 2 or 3 pclkb 0008 b32ch sci12 primary control field 1 data register pcf1dr 8 8 2 or 3 pclkb 0008 b32dh sci12 secondary control field 1 data register scf1dr 8 8 2 or 3 pclkb 0008 b32eh sci12 control field 1 compare enable register cf1cr 8 8 2 or 3 pclkb 0008 b32fh sci12 control field 1 receive data register cf1rr 8 8 2 or 3 pclkb 0008 b330h sci12 timer control register tcr 8 8 2 or 3 pclkb 0008 b331h sci12 timer mode register tmr 8 8 2 or 3 pclkb 0008 b332h sci12 timer prescaler register tpre 8 8 2 or 3 pclkb 0008 b333h sci12 timer count register tcnt 8 8 2 or 3 pclkb 0008 c000h port0 port direction register pdr 8 8 2 or 3 pclkb 0008 c001h port1 port direction register pdr 8 8 2 or 3 pclkb 0008 c002h port2 port direction register pdr 8 8 2 or 3 pclkb 0008 c003h port3 port direction register pdr 8 8 2 or 3 pclkb 0008 c004h port4 port direction register pdr 8 8 2 or 3 pclkb 0008 c005h port5 port direction register pdr 8 8 2 or 3 pclkb 0008 c00ah porta port direction register pdr 8 8 2 or 3 pclkb 0008 c00bh portb port direction register pdr 8 8 2 or 3 pclkb 0008 c00ch portc port direction register pdr 8 8 2 or 3 pclkb 0008 c00dh portd port direction register pdr 8 8 2 or 3 pclkb 0008 c00eh porte port direction register pdr 8 8 2 or 3 pclkb 0008 c011h porth port direction register pdr 8 8 2 or 3 pclkb 0008 c012h portj port direction register pdr 8 8 2 or 3 pclkb 0008 c020h port0 port output data register podr 8 8 2 or 3 pclkb 0008 c021h port1 port output data register podr 8 8 2 or 3 pclkb 0008 c022h port2 port output data register podr 8 8 2 or 3 pclkb 0008 c023h port3 port output data register podr 8 8 2 or 3 pclkb 0008 c024h port4 port output data register podr 8 8 2 or 3 pclkb 0008 c025h port5 port output data register podr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (10 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 35 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 c02ah porta port output data register podr 8 8 2 or 3 pclkb 0008 c02bh portb port output data register podr 8 8 2 or 3 pclkb 0008 c02ch portc port output data register podr 8 8 2 or 3 pclkb 0008 c02dh portd port output data register podr 8 8 2 or 3 pclkb 0008 c02eh porte port output data register podr 8 8 2 or 3 pclkb 0008 c031h porth port output data register podr 8 8 2 or 3 pclkb 0008 c032h portj port output data register podr 8 8 2 or 3 pclkb 0008 c040h port0 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c041h port1 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c042h port2 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c043h port3 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c044h port4 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c045h port5 port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04ah porta port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04bh portb port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04ch portc port input data regist er pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04dh portd port input data regist er pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c04eh porte port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c051h porth port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c052h portj port input data register pidr 8 8 3 or 4 pclkb cycles when reading, 2 or 3 pclkb cycles when writing 0008 c060h port0 port mode register pmr 8 8 2 or 3 pclkb 0008 c061h port1 port mode register pmr 8 8 2 or 3 pclkb 0008 c062h port2 port mode register pmr 8 8 2 or 3 pclkb 0008 c063h port3 port mode register pmr 8 8 2 or 3 pclkb 0008 c064h port4 port mode register pmr 8 8 2 or 3 pclkb 0008 c065h port5 port mode register pmr 8 8 2 or 3 pclkb 0008 c06ah porta port mode register pmr 8 8 2 or 3 pclkb 0008 c06bh portb port mode register pmr 8 8 2 or 3 pclkb 0008 c06ch portc port mode register pmr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (11 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 36 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 c06dh portd port mode register pmr 8 8 2 or 3 pclkb 0008 c06eh porte port mode register pmr 8 8 2 or 3 pclkb 0008 c071h porth port mode register pmr 8 8 2 or 3 pclkb 0008 c072h portj port mode register pmr 8 8 2 or 3 pclkb 0008 c082h port1 open drain control register 0 odr0 8 8 2 or 3 pclkb 0008 c083h port1 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c085h port2 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c086h port3 open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c087h port3 open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c094h porta open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c095h porta open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c096h portb open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c098h portc open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c099h portc open drain control register 1 odr1 8 8, 16 2 or 3 pclkb 0008 c09ah portd open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c09ch porte open drain control register 0 odr0 8 8, 16 2 or 3 pclkb 0008 c0c0h port0 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c1h port1 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c2h port2 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c3h port3 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c4h port4 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0c5h port5 pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cah porta pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cbh portb pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cch portc pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0cdh portd pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0ceh porte pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0d1h porth pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0d2h portj pull-up control register pcr 8 8 2 or 3 pclkb 0008 c0e1h port1 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e2h port2 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e3h port3 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0e5h port5 drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0eah porta drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0ebh portb drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0ech portc drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0edh portd drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0eeh porte drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0f1h porth drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c0f2h portj drive capacity control register dscr 8 8 2 or 3 pclkb 0008 c11fh mpc write-protect register pwpr 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (12 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 37 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 c120h port port switching register b psrb 8 8 2 or 3 pclkb 0008 c121h port port switching register a psra 8 8 2 or 3 pclkb 0008 c143h mpc p03 pin function control register p03pfs 8 8 2 or 3 pclkb 0008 c145h mpc p05 pin function control register p05pfs 8 8 2 or 3 pclkb 0008 c147h mpc p07 pin function control register p07pfs 8 8 2 or 3 pclkb 0008 c14ah mpc p12 pin function control register p12pfs 8 8 2 or 3 pclkb 0008 c14bh mpc p13 pin function control register p13pfs 8 8 2 or 3 pclkb 0008 c14ch mpc p14 pin function control register p14pfs 8 8 2 or 3 pclkb 0008 c14dh mpc p15 pin function control register p15pfs 8 8 2 or 3 pclkb 0008 c14eh mpc p16 pin function control register p16pfs 8 8 2 or 3 pclkb 0008 c14fh mpc p17 pin function control register p17pfs 8 8 2 or 3 pclkb 0008 c150h mpc p20 pin function control register p20pfs 8 8 2 or 3 pclkb 0008 c151h mpc p21 pin function control register p21pfs 8 8 2 or 3 pclkb 0008 c156h mpc p26 pin function control register p26pfs 8 8 2 or 3 pclkb 0008 c157h mpc p27 pin function control register p27pfs 8 8 2 or 3 pclkb 0008 c158h mpc p30 pin function control register p30pfs 8 8 2 or 3 pclkb 0008 c159h mpc p31 pin function control register p31pfs 8 8 2 or 3 pclkb 0008 c15ah mpc p32 pin function control register p32pfs 8 8 2 or 3 pclkb 0008 c15ch mpc p34 pin function control register p34pfs 8 8 2 or 3 pclkb 0008 c160h mpc p40 pin function control register p40pfs 8 8 2 or 3 pclkb 0008 c161h mpc p41 pin function control register p41pfs 8 8 2 or 3 pclkb 0008 c162h mpc p42 pin function control register p42pfs 8 8 2 or 3 pclkb 0008 c163h mpc p43 pin function control register p43pfs 8 8 2 or 3 pclkb 0008 c164h mpc p44 pin function control register p44pfs 8 8 2 or 3 pclkb 0008 c165h mpc p45 pin function control register p45pfs 8 8 2 or 3 pclkb 0008 c166h mpc p46 pin function control register p46pfs 8 8 2 or 3 pclkb 0008 c167h mpc p47 pin function control register p47pfs 8 8 2 or 3 pclkb 0008 c16ch mpc p54 pin function control register p54pfs 8 8 2 or 3 pclkb 0008 c16dh mpc p55 pin function control register p55pfs 8 8 2 or 3 pclkb 0008 c190h mpc pa0 pin function control register pa0pfs 8 8 2 or 3 pclkb 0008 c191h mpc pa1 pin function control register pa1pfs 8 8 2 or 3 pclkb 0008 c192h mpc pa2 pin function control register pa2pfs 8 8 2 or 3 pclkb 0008 c193h mpc pa3 pin function control register pa3pfs 8 8 2 or 3 pclkb 0008 c194h mpc pa4 pin function control register pa4pfs 8 8 2 or 3 pclkb 0008 c195h mpc pa5 pin function control register pa5pfs 8 8 2 or 3 pclkb 0008 c196h mpc pa6 pin function control register pa6pfs 8 8 2 or 3 pclkb 0008 c198h mpc pb0 pin function control register pb0pfs 8 8 2 or 3 pclkb 0008 c199h mpc pb1 pin function control register pb1pfs 8 8 2 or 3 pclkb 0008 c19ah mpc pb2 pin function control register pb2pfs 8 8 2 or 3 pclkb 0008 c19bh mpc pb3 pin function control register pb3pfs 8 8 2 or 3 pclkb 0008 c19ch mpc pb4 pin function control register pb4pfs 8 8 2 or 3 pclkb 0008 c19dh mpc pb5 pin function control register pb5pfs 8 8 2 or 3 pclkb 0008 c19eh mpc pb6 pin function control register pb6pfs 8 8 2 or 3 pclkb 0008 c19fh mpc pb7 pin function control register pb7pfs 8 8 2 or 3 pclkb 0008 c1a2h mpc pc2 pin function control register pc2pfs 8 8 2 or 3 pclkb 0008 c1a3h mpc pc3 pin function control register pc3pfs 8 8 2 or 3 pclkb 0008 c1a4h mpc pc4 pin function control register pc4pfs 8 8 2 or 3 pclkb 0008 c1a5h mpc pc5 pin function control register pc5pfs 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (13 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 38 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 c1a6h mpc pc6 pin function control register pc6pfs 8 8 2 or 3 pclkb 0008 c1a7h mpc pc7 pin function control register pc7pfs 8 8 2 or 3 pclkb 0008 c1a8h mpc pd0 pin function control register pd0pfs 8 8 2 or 3 pclkb 0008 c1a9h mpc pd1 pin function control register pd1pfs 8 8 2 or 3 pclkb 0008 c1aah mpc pd2 pin function control register pd2pfs 8 8 2 or 3 pclkb 0008 c1b0h mpc pe0 pin function control register pe0pfs 8 8 2 or 3 pclkb 0008 c1b1h mpc pe1 pin function control register pe1pfs 8 8 2 or 3 pclkb 0008 c1b2h mpc pe2 pin function control register pe2pfs 8 8 2 or 3 pclkb 0008 c1b3h mpc pe3 pin function control register pe3pfs 8 8 2 or 3 pclkb 0008 c1b4h mpc pe4 pin function control register pe4pfs 8 8 2 or 3 pclkb 0008 c1b5h mpc pe5 pin function control register pe5pfs 8 8 2 or 3 pclkb 0008 c1c8h mpc ph0 pin function control register ph0pfs 8 8 2 or 3 pclkb 0008 c1c9h mpc ph1 pin function control register ph1pfs 8 8 2 or 3 pclkb 0008 c1cah mpc ph2 pin function control register ph2pfs 8 8 2 or 3 pclkb 0008 c1cbh mpc ph3 pin function control register ph3pfs 8 8 2 or 3 pclkb 0008 c1d1h mpc pj1 pin function control register pj1pfs 8 8 2 or 3 pclkb 0008 c1d6h mpc pj6 pin function control register pj6pfs 8 8 2 or 3 pclkb 0008 c1d7h mpc pj7 pin function control register pj7pfs 8 8 2 or 3 pclkb 0008 c290h system reset status register 0 rstsr0 8 8 4 or 5 pclkb 0008 c291h system reset status register 1 rstsr1 8 8 4 or 5 pclkb 0008 c293h system main clock oscillator forced oscillation control register mofcr 8 8 4 or 5 pclkb 0008 c297h system voltage monitoring circuit control register lvcmpcr 8 8 4 or 5 pclkb 0008 c298h system voltage detection level select register lvdlvlr 8 8 4 or 5 pclkb 0008 c29ah system voltage monitoring 1 circuit control register 0 lvd1cr0 8 8 4 or 5 pclkb 0008 c29bh system voltage monitoring 2 circuit control register 0 lvd2cr0 8 8 4 or 5 pclkb 0008 c400h rtc 64-hz counter r64cnt 8 8 2 or 3 pclkb 0008 c402h rtc second counter rseccnt 8 8 2 or 3 pclkb 0008 c402h rtc binary counter 0 bcnt0 8 8 2 or 3 pclkb 0008 c404h rtc minute counter rmincnt 8 8 2 or 3 pclkb 0008 c404h rtc binary counter 1 bcnt1 8 8 2 or 3 pclkb 0008 c406h rtc hour counter rhrcnt 8 8 2 or 3 pclkb 0008 c406h rtc binary counter 2 bcnt2 8 8 2 or 3 pclkb 0008 c408h rtc day-of-week counter rwkcnt 8 8 2 or 3 pclkb 0008 c408h rtc binary counter 3 bcnt3 8 8 2 or 3 pclkb 0008 c40ah rtc date counter rdaycnt 8 8 2 or 3 pclkb 0008 c40ch rtc month counter rmoncnt 8 8 2 or 3 pclkb 0008 c40eh rtc year counter ryrcnt 16 16 2 or 3 pclkb 0008 c410h rtc second alarm register rsecar 8 8 2 or 3 pclkb 0008 c410h rtc binary counter 0 alarm register bcnt0ar 8 8 2 or 3 pclkb 0008 c412h rtc minute alarm register rminar 8 8 2 or 3 pclkb 0008 c412h rtc binary counter 1 alarm register bcnt1ar 8 8 2 or 3 pclkb 0008 c414h rtc hour alarm register rhrar 8 8 2 or 3 pclkb 0008 c414h rtc binary counter 2 alarm register bcnt2ar 8 8 2 or 3 pclkb 0008 c416h rtc day-of-week alarm register rwkar 8 8 2 or 3 pclkb 0008 c416h rtc binary counter 3 alarm register bcnt3ar 8 8 2 or 3 pclkb 0008 c418h rtc date alarm register rdayar 8 8 2 or 3 pclkb 0008 c418h rtc binary counter 0 alarm enable register bcnt0aer 8 8 2 or 3 pclkb table 4.1 list of i/o register s (address order) (14 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 39 of 116 oct 30, 2015 rx130 group 4. i/o registers 0008 c41ah rtc month alarm register rmonar 8 8 2 or 3 pclkb 0008 c41ah rtc binary counter 1 alarm enable register bcnt1aer 8 8 2 or 3 pclkb 0008 c41ch rtc year alarm register ryrar 16 16 2 or 3 pclkb 0008 c41ch rtc binary counter 2 alarm enable register bcnt2aer 16 16 2 or 3 pclkb 0008 c41eh rtc year alarm enable register ryraren 8 8 2 or 3 pclkb 0008 c41eh rtc binary counter 3 alarm enable register bcnt3aer 8 8 2 or 3 pclkb 0008 c422h rtc rtc control register 1 rcr1 8 8 2 or 3 pclkb 0008 c424h rtc rtc control register 2 rcr2 8 8 2 or 3 pclkb 0008 c426h rtc rtc control register 3 rcr3 8 8 2 or 3 pclkb 0008 c42eh rtc time error adjustment register radj 8 8 2 or 3 pclkb 0008 c580h cmpb comparator b control register 1 cpbcnt1 8 8 2 or 3 pclkb 0008 c581h cmpb comparator b control register 2 cpbcnt2 8 8 2 or 3 pclkb 0008 c582h cmpb comparator b flag register cpbflg 8 8 2 or 3 pclkb 0008 c583h cmpb comparator b interrupt control register cpbint 8 8 2 or 3 pclkb 0008 c584h cmpb comparator b filter select register cpbf 8 8 2 or 3 pclkb 0008 c585h cmpb comparator b mode select register cpbmd 8 8 2 or 3 pclkb 0008 c586h cmpb comparator b reference input voltage select register cpbref 8 8 2 or 3 pclkb 0008 c587h cmpb comparator b output control register cpbocr 8 8 2 or 3 pclkb 000a 0900h ctsu ctsu control register 0 ctsucr0 8 8 1 or 2 pclkb 000a 0901h ctsu ctsu control register 1 ctsucr1 8 8 1 or 2 pclkb 000a 0902h ctsu ctsu synchronous noise reduction setting register ctsusdprs 8 8 1 or 2 pclkb 000a 0903h ctsu ctsu sensor stabilization wait control register ctsusst 8 8 1 or 2 pclkb 000a 0904h ctsu ctsu measurement channel register 0 ctsumch0 8 8 1 or 2 pclkb 000a 0905h ctsu ctsu measurement channel register 1 ctsumch1 8 8 1 or 2 pclkb 000a 0906h ctsu ctsu channel enable control register 0 ctsuchac0 8 8 1 or 2 pclkb 000a 0907h ctsu ctsu channel enable control register 1 ctsuchac1 8 8 1 or 2 pclkb 000a 0908h ctsu ctsu channel enable control register 2 ctsuchac2 8 8 1 or 2 pclkb 000a 0909h ctsu ctsu channel enable control register 3 ctsuchac3 8 8 1 or 2 pclkb 000a 090ah ctsu ctsu channel enable control register 4 ctsuchac4 8 8 1 or 2 pclkb 000a 090bh ctsu ctsu channel transmit/receive control register 0 ctsuchtrc 0 8 8 1 or 2 pclkb 000a 090ch ctsu ctsu channel transmit/receive control register 1 ctsuchtrc 1 8 8 1 or 2 pclkb 000a 090dh ctsu ctsu channel transmit/receive control register 2 ctsuchtrc 2 8 8 1 or 2 pclkb 000a 090eh ctsu ctsu channel transmit/receive control register 3 ctsuchtrc 3 8 8 1 or 2 pclkb 000a 090fh ctsu ctsu channel transmit/receive control register 4 ctsuchtrc 4 8 8 1 or 2 pclkb 000a 0910h ctsu ctsu high-pass noise reduction control register ctsudclkc 8 8 1 or 2 pclkb 000a 0911h ctsu ctsu status register ctsust 8 8 1 or 2 pclkb 000a 0912h ctsu ctsu high-pass noise reduction spectrum diffusion control register ctsussc 16 16 1 or 2 pclkb 000a 0914h ctsu ctsu sensor offset register 0 ctsuso0 16 16 1 or 2 pclkb 000a 0916h ctsu ctsu sensor offset register 1 ctsuso1 16 16 1 or 2 pclkb 000a 0918h ctsu ctsu sensor counter ctsusc 16 16 1 or 2 pclkb 000a 091ah ctsu ctsu reference counter ctsurc 16 16 1 or 2 pclkb 000a 091ch ctsu ctsu error status register ctsuerrs 16 16 1 or 2 pclkb 007f c090h flash e2 dataflash control register dflctl 8 8 2 or 3 fclk 007f c0ach temps temperature sensor calibration data register tscdrl 8 8 1 or 2 pclkb 007f c0adh temps temperature sensor calibration data register tscdrh 8 8 1 or 2 pclkb 007f c0b0h flash flash start-up setting monitor register fscmr 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (15 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 40 of 116 oct 30, 2015 rx130 group 4. i/o registers note 1. odd addresses cannot be accessed in 16-bit units. when a ccessing a register in 16-bit units, access the address of the t mr0 or tmr2 register. table 22.4 lists register allocation for 16-bit access. 007f c0b2h flash flash access window start address monitor register fawsmr 16 16 2 or 3 pclkb 007f c0b4h flash flash access window end address monitor register fawemr 16 16 2 or 3 pclkb 007f c0b6h flash flash initial setting register fisr 8 8 2 or 3 pclkb 007f c0b7h flash flash extra area control register fexcr 8 8 2 or 3 pclkb 007f c0b8h flash flash error address monitor register l feaml 16 16 2 or 3 pclkb 007f c0bah flash flash error address monitor register h feamh 8 8 2 or 3 pclkb 007f c0c0h flash protection unlock register fpr 8 8 2 or 3 pclkb 007f c0c1h flash protection unlock status register fpsr 8 8 2 or 3 pclkb 007f c0c2h flash flash read buffer register l frbl 16 16 2 or 3 pclkb 007f c0c4h flash flash read buffer register h frbh 16 16 2 or 3 pclkb 007f ff80h flash flash p/e mode control register fpmcr 8 8 2 or 3 pclkb 007f ff81h flash flash area select register fasr 8 8 2 or 3 pclkb 007f ff82h flash flash processing start address register l fsarl 16 16 2 or 3 pclkb 007f ff84h flash flash processing start address register h fsarh 8 8 2 or 3 pclkb 007f ff85h flash flash control register fcr 8 8 2 or 3 pclkb 007f ff86h flash flash processing end address register l fearl 16 16 2 or 3 pclkb 007f ff88h flash flash processing end address register h fearh 8 8 2 or 3 pclkb 007f ff89h flash flash reset register fresetr 8 8 2 or 3 pclkb 007f ff8ah flash flash status register 0 fstatr0 8 8 2 or 3 pclkb 007f ff8bh flash flash status register 1 fstatr1 8 8 2 or 3 pclkb 007f ff8ch flash flash write buffer register l fwbl 16 16 2 or 3 pclkb 007f ff8eh flash flash write buffer register h fwbh 16 16 2 or 3 pclkb 007f ffb2h flash flash p/e mode entry register fentryr 16 16 2 or 3 pclkb table 4.1 list of i/o register s (address order) (16 / 16) address module symbol register name register symbol number of bits access size number of access cycles
r01ds0273ej0100 rev.1.00 page 41 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5. electrical characteristics 5.1 absolute maximum ratings caution: permanent damage to the mcu may result if absolute maximum ratings are exceeded. to preclude any malfunctions due to noise interference, insert capacitors of high frequency characteristics between the vcc and vss pins, between the avcc0 and avss0 pins, and between th e vrefh0 and vrefl0 pins. place capacitors of about 0.1 f as close as possible to every power supply pin and use the shortest and heaviest possible traces. connect the vcl pin to a vss pin via a 4.7 f capacitor. the capacitor must be placed close to the pin, refer to section 5.13.1, connecting vcl capacitor and bypass capacitors do not input signals or an i/o pull-up power supply to ports other than 5-v tolerant ports while the device is not powered. the current injection that results from input of such a signal or i/o pull-up may cause malfunction and the abnormal current th at passes in the device at this time may cause degradation of internal elements. even if ?0.3 to +6.5 v is input to 5-v tolerant ports, it will not cause problems such as damage to the mcu. note 1. ports p12, p13, p16, and p17 are 5 v tolerant. note 2. the upper limit of operating temperature is 85c or 105c, depending on the product. for details, refer to section 1.2, list of products. table 5.1 absolute maximum ratings conditions: vss = avss0 = vrefl0 = 0 v item symbol value unit power supply voltage vcc ?0.3 to +6.5 v input voltage ports for 5 v tolerant* 1 v in ?0.3 to +6.5 v ports p40 to p47, ports p03 to p07, ports pj6, pj7 ?0.3 to avcc0+0.3 v ports other than above 0.3 to vcc+0.3 reference power supply voltage vrefh0 ?0.3 to avcc0+0.3 v analog power supply voltage avcc0 ?0.3 to +6.5 v analog input voltage when an000 to an007 ussed v an ?0.3 to avcc0+0.3 v when an016 to an021, an024 to an026 used ?0.3 to vcc+0.3 operating temperature* 2 t opr ?40 to +85 ?40 to +105 c storage temperature t stg ?55 to +125 c
r01ds0273ej0100 rev.1.00 page 42 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. use avcc0 and vcc under the following conditions: avcc0 and vcc can be set individually within the operating range when vcc 2.0 v avcc0 = vcc when vcc ? 2.0 v note 2. when powering on the vcc and avcc0 pins, power them on at the same time or the vcc pin first and then the avcc0 pin. table 5.2 recommended operating voltage conditions item symbol conditions min. typ. max. unit power supply voltages vcc *1, *2 1.8 ? 5.5 v vss ? 0 ? analog power supply voltages avcc0 *1, *2 1.8 ? 5.5 v avss0 ? 0 ? vrefh0 1.8 ? avcc0 vrefl0 ? 0 ?
r01ds0273ej0100 rev.1.00 page 43 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.2 dc characteristics table 5.3 dc characteristics (1) conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage riic input pin (except for smbus) v ih vcc 0.7 ? 5.8 v ports p12, p13, p16, p17 (5 v tolerant) vcc 0.8 ? 5.8 ports p14, p15, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports p54, p55, ports pa0 to pa6, ports pb0 to pb7, ports pc2 to pc7, ports pd0 to pd2, ports pe0 to pe5, ports ph0 to ph3, port pj1, res# vcc 0.8 ? vcc + 0.3 ports p03 to p07, ports p40 to p47, ports pj6, pj7 avcc0 0.8 ? avcc0 + 0.2 riic input pin (except for smbus) v il ?0.3 ? vcc 0.3 ports p03 to p07, ports p40 to p47, ports pj6, pj7 ?0.3 ? avcc0 0.3 ports other than above ?0.3 ? vcc 0.2 riic input pin (except for smbus) ?v t vcc 0.05 ? ? ports p12, p13, p16, p17 (5 v tolerant) vcc 0.05 ? ? ports p03 to p07, ports p40 to p47, ports pj6, pj7 avcc0 0.1 ? ? ports other than above vcc 0.1 ? ? input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v extal (external clock input) vcc 0.8 ? vcc + 0.3 riic input pin (smbus) 2.1 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 extal (external clock input) ?0.3 ? vcc 0.2 riic input pin (smbus) ?0.3 ? 0.8
r01ds0273ej0100 rev.1.00 page 44 of 116 oct 30, 2015 rx130 group 5. electrical characteristics table 5.4 dc characteristics (2) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc < 2.7v, 2.0v avcc0 < 2.7v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions schmitt trigger input voltage ports p12, p13, p16, p17 (5 v tolerant) v ih vcc 0.8 ? 5.8 v ports p14, p15, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports p54, p55, ports pa0 to pa6, ports pb0 to pb7, ports pc2 to pc7, ports pd0 to pd2, ports pe0 to pe5, ports ph0 to ph3, port pj1, res# vcc 0.8 ? vcc + 0.3 ports p03 to p07, ports p40 to p47, ports pj6, pj7 avcc0 0.8 ? avcc0 + 0.3 ports p03 to p07, ports p40 to p47, ports pj6, pj7 v il ?0.3 ? avcc0 0.2 ports other than above ?0.3 ? vcc 0.2 ports p03 to p07, ports p40 to p47, ports pj6, pj7 ?v t avcc0 0.01 ?? ports other than above vcc 0.01 ? ? input level voltage (except for schmitt trigger input pins) md v ih vcc 0.9 ? vcc + 0.3 v extal (external clock input) vcc 0.8 ? vcc + 0.3 md v il ?0.3 ? vcc 0.1 extal (external clock input) ?0.3 ? vcc 0.2 table 5.5 dc characteristics (3) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions input leakage current res#, md, port p35 ? i in ? ??1.0 av in = 0v, vcc three-state leakage cur- rent (off-state) ports for 5-v tolerant ? i tsi ? ??1.0 av in = 0v, 5.8v ports except for 5 v tolerant ? ? 0.2 v in = 0v, vcc input capacitance all input pins (except for port p35) c in ??15pfv in = 0mv, f = 1mhz, t a = 25c port p35 ? ? 30 table 5.6 dc characteristics (4) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc < 5.5v, 2.0v avcc0 < 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions input pull-up resistor all ports (except for port p35) r u 10 20 100 k ? v in = 0 v
r01ds0273ej0100 rev.1.00 page 45 of 116 oct 30, 2015 rx130 group 5. electrical characteristics table 5.7 dc characteristics (5) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol typ. max. unit test conditions supply current* 1 high-speed operating mode normal operating mode no peripheral operation* 2 iclk = 32mhz i cc 3.1 ? ma iclk = 16mhz 2.1 ? iclk = 8mhz 1.6 ? all peripheral operation: normal* 3 iclk = 32mhz 10.0 ? iclk = 16mhz 5.7 ? iclk = 8mhz 3.5 ? all peripheral operation: max.* 3 iclk = 32mhz ? 17.5 sleep mode no peripheral operation* 2 iclk = 32mhz 1.6 ? iclk = 16mhz 1.2 ? iclk = 8mhz 1.1 ? all peripheral operation: normal* 3 iclk = 32mhz 5.3 ? iclk = 16mhz 3.2 ? iclk = 8mhz 2.0 ? deep sleep mode no peripheral operation* 2 iclk = 32mhz 1.0 ? iclk = 16mhz 0.9 ? iclk = 8mhz 0.8 ? all peripheral operation: normal* 3 iclk = 32mhz 4.2 ? iclk = 16mhz 2.5 ? iclk = 8mhz 1.7 ? increase during flash rewrite* 5 2.5 ? middle-speed operating modes normal operating mode no peripheral operation* 6 iclk = 12mhz i cc 1.9 ? ma iclk = 8mhz 1.2 ? iclk = 4mhz 0.6 ? iclk = 1mhz 0.3 ? all peripheral operation: normal* 7 iclk = 12mhz 4.6 ? iclk = 8mhz 3.2 ? iclk = 4mhz 2.0 ? iclk = 1mhz 0.9 ? all peripheral operation: max.* 7 iclk = 12mhz ? 8.2 sleep mode no peripheral operation* 6 iclk = 12mhz i cc 1.2 ? ma iclk = 8mhz 0.8 ? iclk = 4mhz 0.3 ? iclk = 1mhz 0.2 ? all peripheral operation: normal* 7 iclk = 12mhz 2.7 ? iclk = 8mhz 1.9 ? iclk = 4mhz 1.2 ? iclk = 1mhz 0.7 ?
r01ds0273ej0100 rev.1.00 page 46 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. supply current values do not include output charge/discharge current from all pins. the values apply when internal pull- up moss are in the off state. note 2. clock supply to the peripheral functi ons is stopped. this does not include bgo operation. the clock source is pll. fclk and pclk are set to divided by 64. note 3. clocks are supplied to the peripheral functions. this does not include bgo operation. the clock source is pll. fclk and pclk are set to the same frequency as iclk. note 4. values when vcc = 3.3 v. note 5. this is the increase for programming or erasure of the rom or e2 dataflash during program execution. note 6. clock supply to the peripheral function is stopped. the clock source is pll when iclk is 12 mhz, hoco when iclk is 8 mhz , and loco otherwise. fclk and pclk are set to divided by 64. note 7. clocks are supplied to the peripheral f unctions. the clock source is pll when iclk is 12 mhz, hoco when iclk is ( mhz, a nd loco otherwise. fclk and pclk are se t to the same frequency as iclk. note 8. clock supply to the peripheral functions is stopped. the clock source is the sub-clock oscillator. fclk and pclk are set to divided by 64. note 9. clocks are supplied to the peripheral functions. the clock source is the sub-cl ock oscillator. fclk and pclk are set to the same frequency as iclk. note 10. values when the mstpcra.mstpa17 bit (12-bit a/d converter mo dule stop bit) is set to ?transition to the module stop sta te is made?. supply current* 1 middle-speed operating modes deep sleep mode no peripheral operation* 6 iclk = 12 mhz i cc 1.0 ? ma iclk = 8 mhz 0.7 ? iclk = 4 mhz 0.2 ? iclk = 1 mhz 0.1 ? all peripheral operation: normal* 7 iclk = 12 mhz 2.3 ? iclk = 8 mhz 1.6 ? iclk = 4 mhz 1.0 iclk = 1 mhz 0.7 ? increase during flash rewrite* 5 2.5 ? low-speed operating mode normal operating mode no peripheral operation* 8 iclk = 32.768 khz i cc 3.8 ? a all peripheral opera- tion: normal* 10 iclk = 32.768 khz 10.9 ? all peripheral operation: max.* 10 iclk = 32.768 khz ? 29.2 sleep mode no peripheral operation* 8 iclk = 32.768 khz 2.1 ? all peripheral opera- tion: normal* 9 iclk = 32.768 khz 6.0 ? deep sleep mode no peripheral operation* 8 iclk = 32.768 khz 1.6 ? all peripheral operation: normal* 9 iclk = 32.768 khz 5.0 ? item symbol typ. max. unit test conditions
r01ds0273ej0100 rev.1.00 page 47 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.1 voltage dependency in high-speed operating mode (reference data) figure 5.2 voltage dependency in middle-speed operating mode (reference data) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 4 8 12 16 20 ta = 25c, iclk = 32mhz * 1 ta = 105c, iclk = 32mhz * 2 ta = 25c, iclk = 16mhz * 1 ta = 105c, iclk = 16mhz * 2 ta = 25c, iclk = 8mhz * 1 ta = 105c, iclk = 8mhz * 2 vcc (v) icc (ma) note 1. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements of sample cores during product evaluation. note 2. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements for the upper-limit samples during product evaluation. ta = 105 ? , iclk = 32mhz ( ? 2) ta = 25c, iclk = 32mhz * 1 ta = 105c, iclk = 16mhz * 2 ta = 105c, iclk = 8mhz * 2 ta = 25c, iclk = 16mhz * 1 ta = 25c, iclk = 8mhz * 1 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 2 4 6 8 ta = 25c, iclk = 12mhz * 1 ta = 105c, iclk = 12mhz * 2 ta = 25c, iclk = 8mhz * 1 ta = 105c, iclk = 8mhz * 2 ta = 25c, iclk = 4mhz * 1 ta = 105c, iclk = 4mhz * 2 ta = 25c, iclk = 1mhz * 1 ta = 105c, iclk = 1mhz * 2 vcc (v) icc (ma) ta = 25c, iclk = 12mhz * 1 ta = 25c, iclk = 8mhz * 1 ta = 25c, iclk = 4mhz * 1 ta = 25c, iclk = 1mhz * 1 ta = 105c, iclk = 12mhz * 2 ta = 105c, iclk = 8mhz * 2 ta = 105c, iclk = 4mhz * 2 ta = 105c, iclk = 1mhz * 2 note 1. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements of sample cores during product evaluation. note 2. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements for the upper-limit samples during product evaluation.
r01ds0273ej0100 rev.1.00 page 48 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.3 voltage dependency in low-speed operating mode (reference data) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 5 10 15 20 25 30 ta = 25c, iclk = 32.768khz * 1 ta = 105c, iclk = 32.768khz * 2 vcc (v) icc (ua) ta = 25c, iclk = 32.768khz * 1 ta = 105c, iclk = 32.768khz * 2 note 1. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements of sample cores during product evaluation. note 2. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements for the upper-limit samples during product evaluation.
r01ds0273ej0100 rev.1.00 page 49 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. supply current values are with all output pins unloaded and all input pull-up moss in the off state. note 2. the iwdt, lvd, and cmpb are stopped. note 3. vcc = 3.3 v. note 4. includes the oscillation circuit. figure 5.4 voltage dependency in software standby mode (reference data) table 5.8 dc characteristics (6) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol typ.* 3 max. unit test conditions supply current* 1 software standby mode* 2 t a = 25c i cc 0.37 0.71 a t a = 55c 0.50 1.70 t a = 85c 1.20 8.00 t a = 105c 2.30 19.60 increment for rtc operation* 4 0.40 ? rcr3.rtcdv[2:0] set to low drive capacity 1.21 ? rcr3.rtcdv[2:0] set to normal drive capacity increment for low-power timer operation 0.37 ? lptcr1.lpcntcksel set to iwdt- dedicated on-chip oscillator increment for independent watchdog timer operation 0.37 ? 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 0.1 1 10 100 ta = 25c * 1 ta = 55c * 1 ta = 85c * 1 ta = 105c * 1 ta = 25c * 2 ta = 55c * 2 ta = 85c * 2 ta = 105c * 2 vcc (v) icc (a) ta = 105c * 2 ta = 105c * 1 ta = 85c * 2 ta = 85c * 1 ta = 55c * 2 ta = 55c * 1 ta = 25c * 2 ta = 25c * 1 note 1. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements of sample cores during product evaluation. note 2. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements for the upper-limit samples during product evaluation.
r01ds0273ej0100 rev.1.00 page 50 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.5 temperature dependency in software standby mode (reference data) note: please contact a renesas electronics sales office for informat ion on the derating of the g-version product. derating is th e systematic reduction of l oad to improve reliability. note 1. total power dissipated by the ent ire chip (including output currents) table 5.9 dc characteristics (7) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v item symbol min. typ. max. unit test conditions permissible total power consumption* 1 p d ?? 300mwd version ?? 105 g version - 4 0- 2 0 0 2 04 06 08 01 0 0 0.1 1 10 100 ta (c) icc ( a) * 1 * 2 note 1. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements of sample cores during product evaluation. note 2. all peripheral operations are operating (normal operation). except bgo operation this is the average of the actual measurements for the upper-limit samples during product evaluation.
r01ds0273ej0100 rev.1.00 page 51 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. the value of the d/a converter is the value of the power supply current including the reference current. note 2. current consumed only by the comparator b module. note 3. icurrent consumed by the power supply (vcc). note 4. when vcc = avcc0 = 3.3 v. note 1. when ofs1.(faststup, lvdas) = 11b. note 2. when ofs1.(faststup, lvdas) = 01b. note 3. when ofs1.lvdas = 0. note 4. turn on the power supply voltage according to the normal startup rising gradient because the register settings set by of s1 are not read in boot mode. table 5.10 dc characteristics (8) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ.* 4 max. unit test conditions analog power supply current during a/d conversion (at high-speed conversion) i avcc ?0.71.7ma during a/d conversion (at low-speed conversion) ? 0.6 1.0 during d/a conversion (per channel)* 1 ??1.5 waiting for a/d and d/a conversion (all units) ? ? 0.4 a reference power supply current during a/d conversion (at high-speed conversion) i refh0 ?25150 a waiting for a/d conversion (all units) ? ? 60 na lvd0 ? i lvd ?0.1? a lvd1, 2 per channel ? 0.15 ? a temperature sensor* 3 ?i temp ?75? a comparator b operating cur- rent* 3 window mode i cmp * 2 ? 12.5 28.6 a comparator high-speed mode ? 3.2 16.2 a comparator low-speed mode ? 1.7 4.4 a cusu operating current during measurement (cpu is in sleep mode) base clock: 2 mhz pin capacity: 50 pf i ctsu ?150? a table 5.11 dc characteristics (9) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions ram standby voltage v ram 1.8 ? ? v table 5.12 dc characteristics (10) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions power-on vcc rising gradient at normal startup* 1 srvcc 0.02 ? 20 ms/v during fast startup time* 2 0.02 ? 2 voltage monitoring 0 reset enabled at startup* 3, * 4 0.02 ? ?
r01ds0273ej0100 rev.1.00 page 52 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.6 ripple waveform note: the recommended capacitance is 4.7 f. variations in connected capacitors should be within the above range. table 5.13 dc characteristics (11) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c the ripple voltage must meet the allowable ripple frequency f r (vcc) within the range between the vcc upper limit and lower limit. when vcc change exceeds vcc 10%, the allowable voltage change rising/falling gradient dt/dvcc must be met. item symbol min. typ. max. unit test conditions allowable ripple frequency f r (vcc) ? ? 10 khz figure 5.6 v r (vcc) vcc 0.2 ? ? 1 mhz figure 5.6 v r (vcc) vcc 0.08 ? ? 10 mhz figure 5.6 v r (vcc) vcc 0.06 allowable voltage change rising/falling gradient dt/dvcc 1.0 ? ? ms/v when vcc change exceeds vcc 10% table 5.14 dc characteristics (12) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. typ. max. unit test conditions permissible error of vcl pin external capacitance c vcl 1.4 4.7 7.0 f v r(vcc) vcc 1 / f r(vcc)
r01ds0273ej0100 rev.1.00 page 53 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: do not exceed the permissible total supply current. table 5.15 permissible output currents (1) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +85c item symbol max. unit permissible output low current (average value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 i ol 4.0 ma ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current (maximum value per pin) ports p03 to p07, ports p40 to p47, ports pj6, pj7 4.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of ports p03 to p07, ports p40 to p47, port pj6, pj7 ? i ol 40 total of ports p12 to p17, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports ph2, ph3, port pj1 40 total of ports p54, p55, ports pb0 to pb7, ports pc2 to pc7, ports ph0, ph1 40 total of ports pa0 to pa6, ports pd0 to pd2, ports pe0 to pe5 40 total of all output pins 80 permissible output high current (average value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 i oh ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current (maximum value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current total of ports p03 to p07, ports p40 to p47, port pj6, pj7 ? i oh ?40 total of ports p12 to p17, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports ph2, ph3, port pj1 ?40 total of ports p54, p55, ports pb0 to pb7, ports pc2 to pc7, ports ph0, ph1 ?40 total of ports pa0 to pa6, ports pd0 to pd2, ports pe0 to pe5 ?40 total of all output pins ?80
r01ds0273ej0100 rev.1.00 page 54 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: do not exceed the permissible total supply current. table 5.16 permissible output currents (2) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c item symbol max. unit permissible output low current (average value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 i ol 4.0 ma ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current (maximum value per pin) ports p03 to p07, ports p40 to p47, ports pj6, pj7 4.0 ports other than above normal output mode 4.0 high-drive output mode 8.0 permissible output low current total of ports p03 to p07, ports p40 to p47, port pj6, pj7 ? i ol 30 total of ports p12 to p17, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports ph2, ph3, port pj1 30 total of ports p54, p55, ports pb0 to pb7, ports pc2 to pc7, ports ph0, ph1 30 total of ports pa0 to pa6, ports pd0 to pd2, ports pe0 to pe5 30 total of all output pins 60 permissible output high current (average value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 i oh ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current (maximum value per pin) ports p40 to p47, ports p03 to p07, ports pj6, pj7 ?4.0 ports other than above normal output mode ?4.0 high-drive output mode ?8.0 permissible output high current total of ports p03 to p07, ports p40 to p47, port pj6, pj7 ? i oh ?30 total of ports p12 to p17, ports p20, p21, p26, p27, ports p30 to p32, p34 to p37, ports ph2, ph3, port pj1 ?30 total of ports p54, p55, ports pb0 to pb7, ports pc2 to pc7, ports ph0, ph1 ?30 total of ports pa0 to pa6, ports pd0 to pd2, ports pe0 to pe5 ?30 total of all output pins ?60
r01ds0273ej0100 rev.1.00 page 55 of 116 oct 30, 2015 rx130 group 5. electrical characteristics table 5.17 output values of voltage (1) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc < 2.7v, 2.0v avcc0 < 2.7v, vss = avss0 = 0v, ta = ?40 to +105c item symbol min. max. unit test conditions output low all output ports (except for riic) normal output mode v ol ?0.8vi ol = 0.5 ma high-drive output mode ? 0.8 i ol = 1.0 ma output high all output ports normal output mode p03 to p07, p40 to p47, pj6, pj7 v oh avcc0 ? 0.5 ? v i oh = ?0.5 ma ports other than above vcc ? 0.5 ? high-drive output mode vcc ? 0.5 ? i oh = ?1.0 ma table 5.18 output values of voltage (2) conditions: 2.7 v vcc < 4.0 v, 2.7 v avcc0 < 4.0 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output ports (except for riic) normal output mode v ol ?0.8vi ol = 1.0 ma high-drive output mode ? 0.8 i ol = 2.0 ma riic pins standard mode (normal output mode) ?0.4 i ol = 3.0 ma fast mode (high-drive output mode) ?0.4 i ol = 6.0 ma output high all output ports normal output mode p03 to p07, p40 to p47, pj6, pj7 v oh avcc0 ? 0.8 ? v i oh = ?1.0 ma ports other than above vcc ? 0.8 ? high-drive output mode vcc ? 0.8 ? i oh = ?2.0 ma table 5.19 output values of voltage (3) conditions: 4.0 v vcc 5.5 v, 4.0 v avcc0 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol min. max. unit test conditions output low all output ports (except for riic) normal output mode v ol ?0.8vi ol = 2.0 ma high-drive output mode ? 0.8 i ol = 4.0 ma riic pins standard mode (normal output mode) ?0.4 i ol = 3.0 ma fast mode (high-drive output mode) ?0.6 i ol = 6.0 ma output high all output ports normal output mode p03 to p07, p40 to p47, pj6, pj7 v oh vcc ? 0.8 ? v i oh = ?2.0 ma ports other than above high-drive output mode vcc ? 0.8 ? i oh = ?4.0 ma
r01ds0273ej0100 rev.1.00 page 56 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.2.1 normal i/o pin out put characteristics (1) figure 5.7 to figure 5.11 show the characteristics when normal output is selected by th e drive capacity control register. figure 5.7 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when normal output is selected (reference data) figure 5.8 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.8 v when normal output is selected (reference data) 0123456 -60 -50 -40 -30 -20 -10 0 10 20 30 40 50 i ho /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc=5.5v vcc=5.5v vcc=3.3v vcc=3.3v vcc=2.7v vcc=2.7v vcc=1.8v vcc=1.8v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 -8 -6 -4 -2 0 2 4 6 8 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 57 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.9 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when normal output is selected (reference data) figure 5.10 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when normal output is selected (reference data) 0 0.5 1 1.5 2 2.5 3 -20 -15 -10 -5 0 5 10 15 20 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ? 00 . 511 . 522 . 533 . 5 -30 -20 -10 0 10 20 30 i oh /i ol vs v oh /v ol v oh /v ol [v] v ih /v il [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 58 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.11 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when normal output is selected (reference data) 0123456 -60 -40 -20 0 20 40 60 ioh/iol vs voh/vol voh/vol [v] ioh/iol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 59 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.2.2 normal i/o pin out put characteristics (2) figure 5.12 to figure 5.16 show the characteristics when high-drive output is select ed by the drive capacity control register. figure 5.12 v oh /v ol and i oh /i ol voltage characteristics at t a = 25c when high-drive output is selected (reference data) figure 5.13 v oh /v ol and i oh /i ol temperature characteristics at vcc = 1.8 v when high-drive output is selected (reference data) 0123456 -150 -100 -50 0 50 100 150 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] vcc=3.3v vcc=3.3v vcc=2.7v vcc=2.7v vcc=1.8v vcc=1.8v vcc=5.5v vcc=5.5v 0 0.20.40.60.8 1 1.21.41.61.8 2 -16 -12 -8 -4 0 4 8 12 16 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 60 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.14 v oh /v ol and i oh /i ol temperature characteristics at vcc = 2.7 v when high-drive output is selected (reference data) figure 5.15 v oh /v ol and i oh /i ol temperature characteristics at vcc = 3.3 v when high-drive output is selected (reference data) 0 0.5 1 1.5 2 2.5 3 -50 -40 -30 -20 -10 0 10 20 30 40 50 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ? 0 0.5 1 1.5 2 2.5 3 3.5 -60 -40 -20 0 20 40 60 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 61 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.16 v oh /v ol and i oh /i ol temperature characteristics at vcc = 5.5 v when high-drive output is selected (reference data) 0123456 -150 -100 -50 0 50 100 150 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ? ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 62 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.2.3 normal i/o pin out put characteristics (3) figure 5.17 to figure 5.20 show the characteristics of the riic output pin. figure 5.17 v ol and i ol voltage characteristics of riic output pin at t a = 25c (reference data) figure 5.18 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 2.7 v (reference data) 0123456 0 20 40 60 80 100 120 i ol vs v ol v ol [v] i ol [ma] vcc=3.3v vcc=2.7v vcc=5.5v 00 . 511 . 522 . 53 0 5 10 15 20 25 30 35 40 i ol vs v ol v ol [v] i ol [ma] ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 63 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.19 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 3.3 v (reference data) figure 5.20 v ol and i ol temperature characteristics of riic outp ut pin at vcc = 5.5 v (reference data) 0 0.5 1 1.5 2 2.5 3 3.5 0 10 20 30 40 50 60 i ol vs v ol v ol [v] i ol [ma] ta=-40 ? ta=25 ? ta=105 ? 0123456 0 20 40 60 80 100 120 140 i oh /i ol vs v oh /v ol v oh /v ol [v] i oh /i ol [ma] ta=-40 ? ta=25 ? ta=105 ?
r01ds0273ej0100 rev.1.00 page 64 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.3 ac characteristics 5.3.1 clock timing note 1. the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the a/d converter is in use. note 4. the maximum operating frequency does not include hoco error or pll jitter. see table 5.23, clock timing. note 1. the lower-limit frequency of fclk is 1 mhz during programming or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note 2. the frequency accuracy of fclk should be 3.5%. note 3. the lower-limit frequency of pclkd is 4 mhz at 2.4 v or above and 1 mhz at below 2.4 v when the a/d converter is in use. note 4. the maximum operating frequency does not include hoco error or pll jitter. see table 5.23, clock timing note 1. programming and erasing t he flash memory is impossible. note 2. the a/d converter cannot be used. table 5.20 operating frequency value (high-speed operating mode) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v maximum operating frequency* 4 system clock (iclk) f max 81 63 2m h z flashif clock (fclk)* 1, * 2 81 63 2 peripheral module clock (pclkb) 8 16 32 peripheral module clock (pclkd)* 3 81 63 2 table 5.21 operating frequency value (middle-speed operating mode) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v maximum operating frequency* 4 system clock (iclk) f max 81 21 2m h z flashif clock (fclk)* 1, * 2 81 21 2 peripheral module clock (pclkb) 8 12 12 peripheral module clock (pclkd)* 3 81 21 2 table 5.22 operating frequency value (low-speed operating mode) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol vcc unit 1.8 v vcc < 2.4 v 2.4 v vcc < 2.7 v 2.7 v vcc 5.5 v maximum operating frequency system clock (iclk) f max 32.768 khz flashif clock (fclk)* 1 32.768 peripheral module clock (pclkb) 32.768 peripheral module clock (pclkd)* 2 32.768
r01ds0273ej0100 rev.1.00 page 65 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. time until the clock can be used after the main clock oscillator stop bit (mosccr.most p) is set to 0 (operating). note 2. reference values when an 8-mhz resonator is used. when specifying the main clock oscillator st abilization time, set the moscwtcr register with a stabilization time value that is equal to or greater than the resonator-manufacturer-recommended value. after changing the setting of the mosccr.mostp bit so that the main clock oscillator operates, read the oscovfsr.moovf flag to confirm that is has become 1, and then start using the main clock. note 3. the vcc range should be 2.4 to 5.5 v when the pll is used. note 4. reference value when a 32.768-khz resonator is used. after changing the setting of the sosccr.sostp bit or rcr3.rtcen bit so that the sub-clock oscillator operates, only start using the sub-clock after the s ub-clock oscillation stabilization wait time th at is equal to or greater than the oscillator- manufacturer-recommended value has elapsed. note 5. only 32.768 khz can be used. table 5.23 clock timing conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions extal external clock input cycle time t xcyc 50 ? ? ns figure 5.21 extal external clock input high pulse width t xh 20 ? ? ns extal external clock input low pulse width t xl 20 ? ? ns extal external clock rise time t xr ?? 5 ns extal external clock fall time t xf ?? 5 ns extal external clock input wait time * 1 t xwt 0.5 ? ? s main clock oscillator oscillation frequency * 2 2.4 vcc 35.5 f main 1?20mhz 1.8 vcc < 2.4 1 ? 8 main clock oscillation stabilization time (crystal) * 2 t mainosc ? 3 ? ms figure 5.22 main clock oscillation st abilization time (ceramic resonator) * 2 t mainosc ?50? s loco clock oscillation frequency f loco 3.44 4.0 4.56 mhz loco clock oscillati on stabilization time t loco ??0.5 s figure 5.23 iwdt-dedicated clock oscillation frequency f iloco 12.75 15 17.25 khz iwdt-dedicated clock oscilla tion stabilization time t iloco ??50 s figure 5.24 hoco clock oscillation frequency f hoco (32 mhz) 31.52 32 32.48 mhz t a = ?40 to + 85c 31.68 32 32.32 t a = 0 to + 55c 31.36 32 32.64 t a = ?40 to +105c hoco clock oscillati on stabilization time t hoco ??30 s figure 5.26 pll input frequency * 3 f pllin 4?8mhz pll circuit oscillation frequency * 3 f pll 24 ? 32 mhz pll clock oscillation stabilization time t pll ??50 s figure 5.27 pll free-running oscillation frequency f pllfr ?8?mhz sub-clock oscillator oscillation frequency * 5 f sub ? 32.768 ? khz sub-clock oscillation stabilization time * 4 t subosc ? 0.5 ? s figure 5.28
r01ds0273ej0100 rev.1.00 page 66 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.21 xtal external clock input timing figure 5.22 main clock oscillation start timing figure 5.23 loco clock oscillation start timing figure 5.24 iwdt-dedicated cl ock oscillation start timing t xh t xcyc xtal external clock input vcc 0.5 t xl t xr t xf main clock oscillator output mosccr.mostp t mainosc loco clock oscillator output lococr.lcstp t loco iwdt-dedicated cloc k oscillator output ilococr.ilcstp t iloco
r01ds0273ej0100 rev.1.00 page 67 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.25 hoco clock osci llation start timing (after reset is canceled by setting ofs1.hocoen bit to 0) figure 5.26 hoco clock os cillation start timing (oscillation is started by setting hococr.hcstp bit) figure 5.27 pll clock oscillation start timing (pll is operated after main cloc k oscillation has settled) figure 5.28 sub-clock oscillation start timing res# internal reset hoco clock ofs1.hocoen t reswt hoco clock hococr.hcstp t hoco pllcr2.pllen pll clock mosccr.mostp t mainosc main clock oscillator output t pll sub-clock oscillator output sosccr.sostp t subosc
r01ds0273ej0100 rev.1.00 page 68 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.3.2 reset timing note 1. when ofs1.(stuplvd1ren, faststup) = 11b. note 2. when ofs1.(stuplvd1ren, faststup) = a value other than 11b. note 3. when iwdtcr.cks[3:0] = 0000b. figure 5.29 reset input timing at power-on figure 5.30 reset input timing (1) figure 5.31 reset input timing (2) table 5.24 reset timing conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions res# pulse width at power-on t reswp 3 ? ? ms figure 5.29 other than above t resw 30 ? ? s figure 5.30 wait time after res# cancellation (at power-on) at normal startup* 1 t reswt ? 8.5 ? ms figure 5.29 during fast startup time* 2 t reswt ? 560 ? s wait time after res# cancellation (during powered-on state) t reswt ? 120 ? s figure 5.30 independent watchdog timer reset period t reswiw ? 1 ? iwdt clock cycle figure 5.31 software reset period t reswsw ? 1 ? iclk cycle wait time after independent watchdog timer reset cancellation* 3 t reswt2 ? 300 ? s wait time after software reset cancellation t reswt2 ? 170 ? s vcc res# t reswp internal reset t reswt res# internal reset t reswt t resw independent watchdog timer reset software reset internal reset t reswt2 t reswiw, t reswsw
r01ds0273ej0100 rev.1.00 page 69 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.3.3 timing of recovery from low power consumption modes note: note values when the frequencies of pclkb, pclkd, and fclk are not divided. note 1. the recovery time varies depending on the state of each osci llator when the wait instructi on is executed. the recovery t ime when multiple oscillators are operating varies depending on the operat ing state of the oscillators that are not selected as the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of pll is 32 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 4. when the frequency of the external clock is 20 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 5. when the frequency of pll is 32 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note: note values when the frequencies of pclkb, pclkd, and fclk are not divided. note 1. the recovery time varies depending on the state of each osci llator when the wait instructi on is executed. the recovery t ime when multiple oscillators are operating varies depending on the operat ing state of the oscillators that are not selected as the system clock source. the above table applies when only the corresponding clock is operating. note 2. when the frequency of the crystal is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 3. when the frequency of pll is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 04h. note 4. when the frequency of the external clock is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. note 5. when the frequency of pll is 12 mhz. when the main clock oscillator wait cont rol register (moscwtcr) is set to 00h. table 5.25 timing of recovery from low power consumption modes (1) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* note: high-speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.32 main clock oscillator and pll circuit operating* 3 t sbypc ?2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex ?3550 s main clock oscillator and pll circuit operating* 5 t sbype ?7095 s sub-clock oscillator operating t sbysc ? 650 800 s hoco clock oscillator operating t sbyho ?4055 s loco clock oscillator operating t sbylo ?4055 s table 5.26 timing of recovery from low power consumption modes (2) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* note: middle- speed mode crystal connected to main clock oscillator main clock oscillator operating* 2 t sbymc ? 2 3 ms figure 5.32 main clock oscillator and pll circuit operating* 3 t sbypc ?2 3ms external clock input to main clock oscillator main clock oscillator operating* 4 t sbyex ?3 4 s main clock oscillator and pll circuit operating* 5 t sbype ?6585 s sub-clock oscillator operating t sbysc ? 600 750 s hoco clock oscillator operating t sbyho ?4050 s loco clock oscillator operating t sbylo ?5 7 s
r01ds0273ej0100 rev.1.00 page 70 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: note values when the frequencies of pclkb, pclkd, and fclk are not divided. note 1. the sub-clock conti nues oscillating in software standby mode during low-speed mode. figure 5.32 software standby mode recovery timing note: note values when the frequencies of pclkb, pclkd, and fclk are not divided. note 1. oscillators continue oscillating in deep sleep mode. note 2. when the frequency of the system clock is 32 mhz. note 3. when the frequency of the system clock is 12 mhz. note 4. when the frequency of the system clock is 32.768 khz. table 5.27 timing of recovery from low power consumption modes (3) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from software standby mode* note: low-speed mode sub-clock oscillator operating t sbysc ? 600 750 s figure 5.32 table 5.28 timing of recovery from low power consumption modes (4) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions recovery time from deep sleep mode* note: high-speed mode* 2 t dslp ?23.5 s figure 5.33 middle-speed mode* 3 t dslp ?3 4 s low-speed mode* 4 t dslp ? 400 500 s oscillator iclk irq software standby mode t sbymc, t sbypc, t sbyex, t sbype, t sbysc, t sbyho, t sbylo
r01ds0273ej0100 rev.1.00 page 71 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.33 deep sleep mode recovery timing note: values when the frequencies of pclkb, pclkd, and fclk are not divided. table 5.29 operating mode transition time conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c mode before transition mode after transition iclk frequency transition time unit min. typ. max. high-speed operating mode middle-speed operating modes 8 mhz ? 10 ? s middle-speed operating modes high-speed operating mode 8 mhz ? 37.5 ? s low-speed operating mode middle-speed operating mode, high-speed operating mode 32.768 khz ? 215 ? s middle-speed operating mode, high-speed operating mode low-speed operating mode 32.768 khz ? 185 ? s oscillator iclk irq deep sleep mode t dslp
r01ds0273ej0100 rev.1.00 page 72 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.3.4 control signal timing note: 200 ns minimum in software standby mode. note 1. t pcyc indicates the cycle of pclkb. note 2. t nmick indicates the cycle of the nmi digital filter sampling clock. note 3. t irqck indicates the cycle of th e irqi digital filter samp ling clock (i = 0 to 7). figure 5.34 nmi interrupt input timing figure 5.35 irq interrupt input timing table 5.30 control signal timing conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. typ. max. unit test conditions nmi pulse width t nmiw 200 ? ? ns nmi digital filter disabled (nmiflte.nflten = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? nmi digital filter enabled (nmiflte.nflten = 1) t nmick 3 200 ns t nmick 3.5* 2 ?? t nmick 3 > 200 ns irq pulse width t irqw 200 ? ? ns irq digital filter disabled (irqflte0.flteni = 0) t pcyc 2 200 ns t pcyc 2* 1 ?? t pcyc 2 > 200 ns 200 ? ? irq digital filter enabled (irqflte0.flteni = 1) t irqck 3 200 ns t irqck 3.5* 3 ?? t irqck 3 > 200 ns nmi t nmiw irq t irqw
r01ds0273ej0100 rev.1.00 page 73 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.3.5 timing of on-chi p peripheral modules table 5.31 timing of on-chip peripheral modules (1) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. max. unit *1 test conditions i/o ports input data pulse width t prw 1.5 ? t pcyc figure 5.36 mtu2 input capture input pulse width single-edge setting t ticw 1.5 ? t pcyc figure 5.37 both-edge setting 2.5 ? input capture input rise/fall time t ticr , t ticf ?0.1 ? s/v timer clock pulse width single-edge setting t tckwh, t tckwl 1.5 ? t pcyc figure 5.38 both-edge setting 2.5 ? phase counting mode 2.5 ? timer clock rise/fall time t tckr , t tckf ?0.1 ? s/v poe2 poe# input pulse width t poew 1.5 ? t pcyc figure 5.39 poe# input rise/fall time t poer , t poef ?0.1 ? s/v tmr timer clock pulse width single-edge setting t tmcwh , t tmcwl 1.5 ? t pcyc figure 5.40 both-edge setting 2.5 ? timer clock rise/fall time t tmcr , t tmcf ?0.1 ? s/v sci input clock cycle time asynchronous t scyc 4?t pcyc figure 5.41 clock synchronous 6 ? input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ?20ns input clock fall time t sckf ?20ns output clock cycle time asynchronous t scyc 16 ? t pcyc figure 5.42 clock synchronous 4 ? output clock pulse width t sckw 0.4 0.6 t scyc output clock rise time t sckr ?20ns output clock fall time t sckf ?20ns transmit data delay time (master) clock synchronous t txd ?40ns transmit data delay time (slave) clock synchronous 2.7 v or above ? 65 ns 1.8 v or above ? 100 ns receive data setup time (master) clock synchronous 2.7 v or above t rxs 65 ? ns 1.8 v or above 90 ? ns receive data setup time (slave) clock synchronous 40 ? ns receive data hold time clock synchronous t rxh 40 ? ns a/d converter trigger input pulse width t trgw 1.5 ? t pcyc figure 5.43 cac cacref input pulse width t pcyc t cac *2 t cacref 4.5 t cac + 3 t pcyc ?ns t pcyc > t cac *2 5 t cac + 6.5 t pcyc cacref input rise/fall time t cacref , t cacreff ?0.1 ? s/v
r01ds0273ej0100 rev.1.00 page 74 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. t cac : cac count clock source cycle note 3. when the loco is selected as the clock output source (ckocr.ckosel[3:0] bits = 000b), set the clock output division rati o selection to divided by 2 (ckocr.ckodiv[2:0] bits = 001b). note 4. when the xtal external clock i nput or an oscillator is used with divided by 1 (ckocr.ckosel[3:0] bits = 010b and ckocr.ckodiv[2:0] bits = 000b) to output from clkout, the abov e should be satisfied with an input duty cycle of 45 to 55%. clkout clkout pin output cycle *4 vcc = 2.7 v or above t ccyc 62.5 ? ns figure 5.44 vcc = 1.8 v or above 125 clkout pin high pulse width *3 vcc = 2.7 v or above t ch 15 ? ns vcc = 1.8 v or above 30 clkout pin low pulse width *3 vcc = 2.7 v or above t cl 15 ? ns vcc = 1.8 v or above 35 clkout pin output rise time vcc = 2.7 v or above t cr ?12ns vcc = 1.8 v or above 25 clkout pin output fall time vcc = 2.7 v or above t cf ?12ns vcc = 1.8 v or above 25 table 5.31 timing of on-chip peripheral modules (1) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. max. unit *1 test conditions
r01ds0273ej0100 rev.1.00 page 75 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. t pcyc : pclk cycle note 2. n: an integer from 1 to 8 that can be set by the rspi clock delay register (spckd) note 3. n: an integer from 1 to 8 that can be set by the rspi slave select negation delay register (sslnd) table 5.32 timing of on-chip peripheral modules (2) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, ta = ?40 to +105c, c = 30 pf, when high-drive output is se lected by the drive capacity register item symbol min. max. unit test conditions rspi rspck clock cycle master t spcyc 2 4096 t pcyc * 1 figure 5.45 slave 8 4096 rspck clock high pulse width master t spckw h (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock low pulse width master t spckw l (t spcyc ? t spckr ? t spckf )/2 ? 3 ?ns slave (t spcyc ? t spckr ? t spckf )/2 ? rspck clock rise/ fall time output 2.7 v or above t spckr, t spckf ?1 0n s 1.8 v or above ? 15 input ? 0.1 s/v data input setup time master 2.7 v or above t su 10 ? ns figure 5.46 to figure 5.49 1.8 v or above 30 ? slave 25 ? t pcyc ? data input hold time master rspck set to a division ratio other than pclkb divided by 2 t h t pcyc ?ns rspck set to pclkb divided by 2 t hf 0? slave t h 20 + 2 t pcyc ? ssl setup time master t lead ?30 + n* 2 t spcyc ?ns slave 2 ? t pcyc ssl hold time master t lag ?30 + n* 3 t spcyc ?ns slave 2 ? t pcyc data output delay time master 2.7 v or above t od ?1 4n s 1.8 v or above ? 30 slave 2.7 v or above ? 3 t pcyc + 65 1.8 v or above ? 3 t pcyc +105 data output hold time master 2.7 v or above t oh 0?n s slave 0 ? successive transmissio n delay time master t td t spcyc + 2 t pcyc 8 t spcyc + 2 t pcyc ns slave 4 t pcyc ? mosi and miso rise/ fall time output 2.7 v or above t dr, t df ?1 0n s 1.8 v or above ? 15 input ? 1 s ssl rise/fall time output 2.7 v or above t sslr, t sslf ?1 0n s 1.8 v or above ? 15 ns input ? 1 s slave access time 2.7 v or above t sa ?6t pcyc figure 5.48, figure 5.49 1.8 v or above ? 7 slave output release time 2.7 v or above t rel ?5t pcyc 1.8 v or above ? 6
r01ds0273ej0100 rev.1.00 page 76 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note 1. t pcyc : pclk cycle table 5.33 timing of on-chip peripheral modules (3) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v , ta = ?40 to +105c item symbol min. max. unit* 1 test conditions simple spi sck clock cycle output (master) t spcyc 4 65536 t pcyc figure 5.45 sck clock cycle input (slave) 6 65536 t pcyc sck clock high pulse width t spckwh 0.4 0.6 t spcyc sck clock low pulse width t spckwl 0.4 0.6 t spcyc sck clock rise/fall time t spckr, t spckf ?20ns data input setup time (master) 2.7 v or above t su 65 ? ns figure 5.46, figure 5.47 1.8 v or above 95 ? data input setup time (slave) 40 ? data input hold time t h 40 ? ns ssl input setup time t lead 3?t spcyc ssl input hold time t lag 3?t spcyc data output delay time (master) t od ?40ns data output delay time (slave) 2.7 v or above ? 65 1.8 v or above ? 100 data output hold time (master) 2.7 v or above t oh ?10 ? ns 1.8 v or above ?20 ? data output hold time (slave) ?10 ? data rise/fall time t dr , t df ?20ns ssl input rise/fall time t sslr , t sslf ?20ns slave access time t sa ?6t pcyc figure 5.48, figure 5.49 slave output release time t rel ?6t pcyc
r01ds0273ej0100 rev.1.00 page 77 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: t iiccyc : riic internal reference count clock (iic ) cycle note 1. the value in parentheses is used when the icmr3.nf[1:0] bits are set to 11b while a digital filter is enabled with the i cfer.nfe bit = 1. note 2. c b is the total capacitance of the bus lines. table 5.34 timing of on-chip peripheral modules (4) conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min.* 1, * 2 max. unit test conditions riic (standard mode, smbus) scl cycle time t scl 6 (12) t iiccyc + 1300 ? ns figure 5.50 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 1000 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 1000 ? ns stop condition setup time t stos 1000 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf riic (fast mode) scl cycle time t scl 6 (12) t iiccyc + 600 ? ns figure 5.50 scl high pulse width t sclh 3 (6) t iiccyc + 300 ? ns scl low pulse width t scll 3 (6) t iiccyc + 300 ? ns scl, sda rise time t sr ? 300 ns scl, sda fall time t sf ? 300 ns scl, sda spike pulse removal time t sp 01 ( 4 ) t iiccyc ns sda bus free time t buf 3 (6) t iiccyc + 300 ? ns start condition hold time t stah t iiccyc + 300 ? ns repeated start condition setup time t stas 300 ? ns stop condition setup time t stos 300 ? ns data setup time t sdas t iiccyc + 50 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0273ej0100 rev.1.00 page 78 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: t pcyc : pclk cycle note 1. c b is the total capacitance of the bus lines. table 5.35 timing of on-chip peripheral modules (5) conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = 0 v, fpclkb 32 mhz, t a = ?40 to +105c item symbol min.* 1 max. unit test conditions simple i 2 c (standard mode) sda rise time t sr ? 1000 ns figure 5.50 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc ns data setup time t sdas 250 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf simple i 2 c (fast mode) sda rise time t sr ? 300 ns figure 5.50 sda fall time t sf ? 300 ns sda spike pulse removal time t sp 04 t pcyc ns data setup time t sdas 100 ? ns data hold time t sdah 0?n s scl, sda capacitive load c b ? 400 pf
r01ds0273ej0100 rev.1.00 page 79 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.36 i/o port input timing figure 5.37 mtu2 input/output timing figure 5.38 mtu2 clock input timing figure 5.39 poe# input timing port pclk t prw pclk t ticw t ticr t ticf output compare output input capture input mtclka to mtclkd pclk t tckwl t tckwh t tckr t tckf pclk t poew t poef t poer poen# input
r01ds0273ej0100 rev.1.00 page 80 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.40 tmr clock input timing figure 5.41 sck clock input timing figure 5.42 sci input/output timing: clock synchronous mode pclk tmci0 to tmci3 t tmcwl t tmcwh t tmcr t tmcf t sckw t sckr t sckf t scyc sckn n = 1, 5, 6, 12 t txd t rxs t rxh txdn rxdn sckn n = 1, 5, 6, 12
r01ds0273ej0100 rev.1.00 page 81 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.43 a/d converter external trigger input timing figure 5.44 clkout output timing figure 5.45 rspi clock timing and simple spi clock timing adtrg0# pclk t trgw t cf t ch t ccyc t cr t cl clkout pin output test conditions: v oh = vcc 0.7, v ol = vcc 0.3, i oh = -1.0 ma, i ol = 1.0 ma, c = 30 pf t spckwh v oh v oh v ol v ol v oh v oh t spckwl t spckr t spckf v ol t spcyc t spckwh v ih v ih v il v il v ih v ih t spckwl t spckr t spckf v il t spcyc v oh = 0.7 vcc, v ol = 0.3 vcc, v ih = 0.7 vcc, v il = 0.3 vcc n = 1, 5, 6, 12 sckn master select output sckn slave select input rspcka master select output rspcka slave select input simple spi rspi
r01ds0273ej0100 rev.1.00 page 82 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.46 rspi timing (master, cpha = 0) and simple spi clock timing (master, ckph = 1) figure 5.47 rspi timing (master, cpha = 1) and simple spi clock timing (master, ckph = 0) t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh t od msb in data lsb in msb in msb out data lsb out idle msb out sckn ckpol = 0 output sckn ckpol = 1 output smison input smosin output n = 1, 5, 6, 12 simple spi rspi ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output ssla0 to ssla3 output rspcka cpol = 0 output rspcka cpol = 1 output misoa input mosia output rspi simple spi sckn ckpol = 1 output sckn ckpol = 0 output smison input smosin output t dr, t df t su t h t lead t td t lag t sslr, t sslf t oh msb in data lsb in msb in msb out data lsb out idle msb out t od n = 1, 5, 6, 12
r01ds0273ej0100 rev.1.00 page 83 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.48 rspi timing (sl ave, cpha = 0) and simple spi clock timing (slave, ckph = 1) figure 5.49 rspi timing (sl ave, cpha = 1) and simple spi clock timing (slave, ckph = 0) t dr, t df t su t h t lead t td t lag t sa msb in data lsb in msb in msb out data lsb out msb in msb out t oh t od t rel sckn ckpol = 0 input sckn ckpol = 1 input smison output smosin input n = 1, 5, 6, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input t dr, t df t sa t oh t lead t td t lag t h lsb out (last data) data msb out msb in data lsb in msb in lsb out t su t od t rel msb out sckn ckpol = 1 input sckn ckpol = 0 input smison output smosin input n = 1, 5, 6, 12 simple spi rspi ssla0 input rspcka cpol = 0 input rspcka cpol = 1 input misoa output mosia input ssn# input
r01ds0273ej0100 rev.1.00 page 84 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.50 riic bus interface input/output timing and simple i 2 c bus interface input/output timing test conditions v ih = vcc 0.7, v il = vcc 0.3 sda scl v ih v il t stah t sclh t scll p *1 s *1 t sf t sr t scl t sdah t sdas t stas t sp t stos p *1 t buf sr *1 note 1. s, p, and sr indicate the following conditions, respectively. s: start condition p: stop condition sr: repeated start condition
r01ds0273ej0100 rev.1.00 page 85 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.4 a/d conversion characteristics figure 5.51 avcc0 to vrefh0 voltage range vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 a/d conversion characteristics (1) a/d conversion characteristics (2) adcsr.adhsc = 1 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 vrefh0 5.0 4.0 3.0 2.0 1.0 1.0 2.0 3.0 4.0 5.0 a/d conversion characteristics (3) a/d conversion characteristics (4) adcsr.adhsc = 0 5.5 2.7 2.4 2.4 2.7 5.5 avcc0 a/d conversion characteristics (5) 1.8 1.8
r01ds0273ej0100 rev.1.00 page 86 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diff erential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.36 a/d conversion characteristics (1) conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, 2.7 v vrefh0 avcc0, reference voltage = vrefh0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 32 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance (max.) = 0.3 k ? 1.41 ? ? s high-precision channel adcsr.adhsc bit = 0 adsstrn = 0dh 2.25 ? ? s normal-precision channel adcsr.adhsc bit = 0 adsstrn = 28h analog input capacitance cs ? ? 15 pf pin capacitance included figure 5.52 analog input resistance rs ? ? 2.5 k ? figure 5.52 analog input effective range 0 ? vrefh0 v offset error ? 0.5 4.5 lsb high-precision channel 6.0 lsb other than above full-scale error ? 0.75 4.5 lsb high-precision channel 6.0 lsb other than above quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb
r01ds0273ej0100 rev.1.00 page 87 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diff erential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.37 a/d conversion characteristics (2) conditions: 2.4 v vcc 5.5 v, 2.4 v avcc0 5.5 v, 2.4 v vrefh0 avcc0, reference voltage = vrefh0, vss = avss0 = vrefl0 = 0 v, t a = ?40 to +105c item min. typ. max. unit test conditions frequency 1 ? 16 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 16 mhz) permissible signal source impedance (max.) = 1.3 k ? 2.82 ? ? s high-precision channel adcsr.adhsc bit = 0 adsstrn = xxh 4.5 ? ? s normal-precision channel adcsr.adhsc bit = 0 adsstrn = xxh analog input capacitance cs ? ? 15 pf analog input resistance rs ? ? 2.5 k ? analog input effective range 0 ? vrefh0 v offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 4.5 lsb
r01ds0273ej0100 rev.1.00 page 88 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diff erential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.38 a/d conversion characteristics (3) conditions: 2.7v vcc 5.5v, 2.7v avcc0 5.5v, 2.7v vrefh0 avcc0, reference voltage = vrefh0, vss = avss0 = vrefl0 = 0v, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 27 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 27 mhz) permissible signal source impedance (max.) = 1.1 k ? 2?? s high-precision channel adcsr.adhsc bit = 1 adsstrn = 0dh 3 ? ? normal-precision channel adcsr.adhsc bit = 1 adsstrn = 28h analog input capacitance cs ? ? 15 pf pin capacitance included analog input resistance rs ? ? 2.5 k ? analog input effective range 0 ? vrefh0 v offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb
r01ds0273ej0100 rev.1.00 page 89 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diff erential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.39 a/d conversion characteristics (4) conditions: 2.4v vcc 5.5v, 2.4v avcc0 5.5v, 2.4v vrefh0 avcc0, reference voltage = vrefh0, vss = avss0 = 0v, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 16 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 12 mhz) permissible signal source impedance (max.) = 2.2 k ? 3.38 ? ? s high-precision channel adcsr.adhsc bit = 1 adsstrn = 0dh 5.06 ? ? normal-precision channel adcsr.adhsc bit = 1 adsstrn = 28h analog input capacitance cs ? ? 15 pf pin capacitance included analog input resistance rs ? ? 2.5 k ? analog input effective range 0 ? vrefh0 v offset error ? 0.5 4.5 lsb full-scale error ? 0.75 4.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 1.25 5.0 lsb high-precision channel 8.0 lsb other than above dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.0 3.0 lsb
r01ds0273ej0100 rev.1.00 page 90 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: the characteristics apply when no pin functions other than a/d converter input are used. absolute accuracy includes quantization errors. offset error, full-scale error, dnl diff erential nonlinearity error, and inl integral nonlinearity error d o not include quantization errors. note 1. the conversion time is the sum of the sampling time and the comparison time. as the test conditions, the number of sampl ing states is indicated. table 5.40 a/d conversion characteristics (5) conditions: 1.8v vcc = avcc0 < 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, 1.8v vrefh0 avcc0, reference voltage = vrefh0, vss = avss0 = vrefl0 = 0v, ta = ?40 to +105c item min. typ. max. unit test conditions frequency 1 8 mhz resolution ? ? 12 bit conversion time* 1 (operation at pclkd = 32 mhz) permissible signal source impedance (max.) = 5 k ? 6.75 ? ? s high-precision channel adcsr.adhsc bit = 1 adsstrn = 0dh 10.13 ? ? normal-precision channel adcsr.adhsc bit = 1 adsstrn = 28h analog input capacitance cs ? ? 15 pf pin capacitance included analog input resistance rs ? ? 2.5 k ? analog input effective range 0 ? vrefh0 v offset error ? 1.0 7.5 lsb full-scale error ? 1.5 7.5 lsb quantization error ? 0.5 ? lsb absolute accuracy ? 3.0 8.0 lsb high-precision channel dnl differential nonlinearity error ? 1.0 ? lsb inl integral nonlinearity error ? 1.25 3.0 lsb table 5.41 a/d converter channel classification classification channel conditions remarks high-precision channel an000 to an007 avcc0 = 1.8 to 5.5 v pins an000 to an007 cannot be used as digital outputs when the a/d converter is in use. normal-precision channel an016 to an021 an024 to an026 internal reference voltage input channel internal reference voltage avcc0 = 2.0 to 5.5 v temperature sensor input channel temperature sensor output avcc0 = 2.0 to 5.5 v
r01ds0273ej0100 rev.1.00 page 91 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.52 equivalent circuit figure 5.53 illustration of a/d converter characteristic terms 12b - adc cs rs r0 mcu integral nonlinearity error (inl) actual a/d conversion characteristic ideal a/d conversion characteristic analog input voltage offset error absolute accuracy differential nonlinearity error (dnl) full-scale error fffh 000h 0 ideal line of actual a/d conversion characteristic 1-lsb width for ideal a/d conversion characteristic differential nonlinearity error (dnl) 1-lsb width for ideal a/d conversion characteristic vrefh0 (full-scale) a/d converter output code
r01ds0273ej0100 rev.1.00 page 92 of 116 oct 30, 2015 rx130 group 5. electrical characteristics absolute accuracy absolute accuracy is the difference between output code based on the theoretical a/d conversion characteristics, and the actual a/d conversion result. when measur ing absolute accuracy, the voltage at th e midpoint of the width of analog input voltage (1-lsb width), that can m eet the expectation of outp utting an equal code based on the theoretical a/d conversion characteristics, is us ed as an analog input voltage. for example, if 12-bit resolution is used and if reference voltage (vrefh0 = 3.072 v), then 1-lsb width becomes 0.75 mv, and 0 mv, 0.75 mv, 1.5 mv, ... are used as analog input voltages. if analog input voltage is 6 mv, absolute accuracy = 5 lsb means that the actual a/d conversion result is in the range of 003h to 00dh though an output code, 008h, can be expect ed from the theoretical a/d conversion characteristics. integral nonlinearity error (inl) integral nonlinearity error is the maximum deviation between the ideal line when the meas ured offset and full-scale errors are zeroed, and the actual output code. differential nonlinearity error (dnl) differential nonlinearity error is the difference between 1-lsb width base d on the ideal a/d conver sion characteristics and the width of the actual output code. offset error offset error is the difference between a transition point of the ideal first output code and the actual first output code. full-scale error full-scale error is the differen ce between a transition point of the ideal last output code and the actual last output code.
r01ds0273ej0100 rev.1.00 page 93 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.5 d/a conversion characteristics 5.6 temperature sensor characteristics table 5.42 d/a conversion characteristics (1) conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, fpclkb 32mhz, t a = ?40 to +105c item symbol min. typ. max. unit test conditions resolution ? ? ? 8 bit conversion time vcc=2.7 to 3.6v t dconv ??3 . 0 s 35-pf capacitive load vcc=1.6 to 2.7v ? ? ? 6.0 absolute accuracy vcc=2.4 to 3.6v ? ? ? 3.0 lsb 2-m ? resistive load vcc=1.8 to 2.4v ? ? ? 3.5 vcc=2.4 to 3.6v ? ? ? 2.0 lsb 4-m ? resistive load vcc=1.8 to 2.4v ? ? ? 2.5 ro output resistance ? ? 6.4 ? k ? table 5.43 temperature sensor characteristics conditions: 2.0 v vcc 5.5 v, 2.0 v avcc0 5.5 v, vss = avss0 = 0 v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions relative accuracy DD 1.5 D c 2.4 v or above D 2.0 D below 2.4 v temperature slope DD ?3.65 D mv/c output voltage (25c) DD 1.05 D v vcc = 3.3 v temperature sensor start time t start DD 5 s sampling time D 5 DD s
r01ds0273ej0100 rev.1.00 page 94 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.7 comparator characteristics table 5.44 comparator characteristics conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions cvrefb0 to cvrefb1 input reference voltage vref 0 ? vcc ? 1.4 v cmpb0 to cmpb1 input voltage vi -0.3 ? vcc + 0.3 v offset comparator high-speed mode ?? ? 50 mv comparator high-speed mode window function enabled ?? ? 60 mv comparator low-speed mode ?? ? 40 mv comparator output delay time comparator high-speed mode td ? ? 1.2 s vcc = 3 v, input slew rate 50 mv/us comparator high-speed mode window function enabled tdw ? ? 2.0 s comparator low-speed mode td ? ? 5.0 s high-side reference voltage (comparator high-speed mode, window function enabled) vrfh ? 0.76 vcc ? v low-side reference voltage (comparator high-speed mode, window function enabled) vrfl ? 0.24 vcc ? v operation stabilization wait time tcmp 100 ? ? s
r01ds0273ej0100 rev.1.00 page 95 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.54 comparator output delay time in comparator high-speed mode and low-speed mode figure 5.55 comparator output delay time in high-speed mode with window function enabled cmpb cmpob td td cvrefb = 0 v cmpb cmpob tdw tdw internal vrh = vcc * 0.76 cmpb cmpob tdw tdw internal vrh = vcc * 0.24
r01ds0273ej0100 rev.1.00 page 96 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.8 ctsu characteristics 5.9 power-on reset circuit and voltage detection circuit characteristics note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd2), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. n in the symbol vdet0_n denotes the value of the lvds1[1:0] bits. note 2. n in the symbol vdet1_n denotes the value of the lvdlvlr.lvd1lvl[3:0] bits. note 3. n in the symbol vdet2_n denotes the value of the lvdlvlr.lvd2lvl[1:0] bits. note 4. vdet2_0 selection can be used only w hen the cmpa2 pin input voltage is selected, and cannot be used when the power suppl y voltage (vcc) is selected. table 5.45 ctsu characteristics conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions external capacitance connected to tscap pin c tscap 91011nf ts pin capacitive load c base ? ? 50 pf permissible output high/low current pb1 to pb7, pc2 to pc7, p54, p55, ph0 to ph3, p12 to p17, p20, p21, p26, p27, p30 to p32, p34, p35 ? ? ? 24 ma when vxsel = 0 pa0 to pa6,pb0, pd0 to pd2, pe0 to pe5 ? ? ? 16 ma when vxsel = 0 table 5.46 power-on reset circuit and volt age detection circuit characteristics (1) conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions voltage detection level power-on reset (por) v por 1.35 1.50 1.65 v figure 5.56, figure 5.57 voltage detection circuit (lvd0)* 1 v det0_0 3.67 3.84 3.97 v figure 5.58 at falling edge vcc v det0_1 2.70 2.82 3.00 v det0_2 2.37 2.51 2.67 v det0_3 1.80 1.90 1.99 voltage detection circuit (lvd1)* 2 v det1_0 4.12 4.29 4.42 v figure 5.59 at falling edge vcc v det1_1 3.98 4.14 4.28 v det1_2 3.86 4.02 4.16 v det1_3 3.68 3.84 3.98 v det1_4 2.99 3.10 3.29 v det1_5 2.89 3.00 3.19 v det1_6 2.79 2.90 3.09 v det1_7 2.68 2.79 2.98 v det1_8 2.57 2.68 2.87 v det1_9 2.47 2.58 2.67 v det1_a 2.37 2.48 2.57 v det1_b 2.10 2.20 2.30 v det1_c 1.86 1.96 2.06 v det1_d 1.80 1.86 1.96 voltage detection level voltage detection circuit (lvd2)* 3 v det2_0 * 4 4.08 4.29 4.48 v figure 5.60 at falling edge vcc v det2_1 3.95 4.14 4.35 v det2_2 3.82 4.02 4.22 v det2_3 3.62 3.84 4.02
r01ds0273ej0100 rev.1.00 page 97 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: these characteristics apply when noise is not superimposed on the power supply. wh en a setting is made so that the voltage detection level overlaps with that of the voltage detection circ uit (lvd1), it cannot be specified which of lvd1 and lvd2 is us ed for voltage detection. note 1. when ofs1.(stuplvd1ren, faststup) = 11b. note 2. when ofs1.(stuplvd1ren, faststup) 11b. note 3. the minimum vcc down time indicates the time when vcc is below the minimum val ue of voltage detection levels v por , v det1 , and v det2 for the por/lvd. figure 5.56 voltage detection reset timing table 5.47 power-on reset circuit and volt age detection circuit characteristics (2) conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions wait time after power-on reset cancellation at normal startup* 1 t por D 9.1 D ms figure 5.57 during fast startup time* 2 t por D 1.6 D wait time after voltage monitoring 0 reset cancellation power-on voltage monitoring 0 reset disabled* 1 t lvd1 D 568 D s figure 5.58 power-on voltage monitoring 0 reset enabled* 2 D 100 D wait time after voltage monitoring 1 reset cancellation t lvd1 D 100 D s figure 5.59 wait time after voltage monitoring 2 reset cancellation t lvd2 D 100 D s figure 5.60 response delay time t det DD 350 s figure 5.56 minimum vcc down time* 3 t voff 350 DD s figure 5.56, vcc = 1.0 v or above power-on reset enable time t w(por) 1 DD ms figure 5.57, vcc = below 1.0 v lvd operation stabilization time (after lvd is enabled) td (e-a) DD 300 s figure 5.59, figure 5.60 hysteresis width (power-on rest (por)) v porh D 110 D mv hysteresis width (lvd1 and lvd2) v lvh D 70 D mv vdet1_4 selected D 60 D vdet1_5 to 9 selected D 50 D vdet1_a to b selected D 40 D vdet1_c to f selected D 60 D lvd2 selected internal reset signal (active-low) vcc t voff t por t det v por t det 1.0v v porh
r01ds0273ej0100 rev.1.00 page 98 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.57 power-on reset timing figure 5.58 voltage detection circuit timing (vdet0) internal reset signal (active-low) vcc t por v por 1.0 v t w(por) *1 t det note 1. t w(por) is the time required for a power-on reset to be enabled while the external power vcc is being held below the valid voltage (1.0 v). when vcc turns on, maintain t w(por) for 1.0 ms or more. v porh t voff v det0 vcc t det t det internal reset signal (active-low) v lvh t lvd0
r01ds0273ej0100 rev.1.00 page 99 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.59 voltage detection circuit timing (v det1 ) figure 5.60 voltage detection circuit timing (v det2 ) t voff v det1 vcc t det t det t lvd1 t d(e-a) lvd1e lvd1 comparator output lvd1cmpe lvd1mon internal reset signal (active-low) when lvd1rn = l when lvd1rn = h v lvh t lvd1 t voff v det2 vcc t det t det t lvd2 t d(e-a) lvd2e lvd2 comparator output lvd2cmpe lvd2mon internal reset signal (active-low) when lvd2rn = l when lvd2rn = h v lvh t lvd2
r01ds0273ej0100 rev.1.00 page 100 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.10 oscillation stop detection timing figure 5.61 oscillation stop detection timing table 5.48 oscillation stop detection timing conditions: 1.8v vcc = avcc0 ? 2.0v, 2.0v vcc 5.5v, 2.0v avcc0 5.5v, vss = avss0 = 0v, t a = ?40 to +105c item symbol min. typ. max. unit test conditions detection time t dr ? ? 1 ms figure 5.61 t dr main clock ostdsr.ostdf low-speed clock ic lk t dr main clock ostdsr.ostdf ic lk when the main clock is selected when the pll clock is selected pll clock low-speed clock
r01ds0273ej0100 rev.1.00 page 101 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.11 rom (flash memory for code storage) characteristics note 1. definition of reprogram/erase cycle: the reprogram/erase cycle is the number of erasing for each block. when the reprogr am/ erase cycle is n times (n = 1000), erasing can be performed n times for each block. for instance, when 4-byte programming is performed 256 times for different addresses in 1-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for se veral times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer and the self-programming library provided from renesas electronics . note 3. this result is obtained from reliability testing. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.49 rom (flash memory for code storage) characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n pec 1000 ? ? times data retention after 1000 times of n pec t drp 20* 2, * 3 ? ? year t a = +85c table 5.50 rom (flash memory for code storage) characteristics (2) high-speed operating mode conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 4-byte t p4 ? 103 931 ? 52 489 s erasure time 1-kbyte t e1k ? 8.23 267 ? 5.48 214 ms 128-kbyte t e128k ? 203 463 ? 20 228 ms blank check time 4-byte t bc4 ? ? 48 ? ? 15.9 s 1-kbyte t bc1k ? ? 1.58 ? ? 0.127 ms erase operation forcible stop time t sed ? ? 21.6 ? ? 12.8 s start-up area switching setting time t sas ? 12.6 543 ? 6.16 432 ms access window time t aws ? 12.6 543 ? 6.16 432 ms rom mode transition wait time 1 t dis 2??2?? s rom mode transition wait time 2 t ms 5??5?? s
r01ds0273ej0100 rev.1.00 page 102 of 116 oct 30, 2015 rx130 group 5. electrical characteristics note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.51 rom (flash memory for code storage) characteristics (3) middle-speed operating mode conditions: 1.8 v vcc = avcc0 ? 2.0 v, 2.0 v vcc 5.5 v, 2.0 v avcc0 5.5 v, vss = avss0 = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 4-byte t p4 ? 143 1330 ? 96.8 932 s erasure time 1-kbyte t e1k ? 8.3 269 ? 5.85 219 ms 128-kbyte t e128k ? 203 464 ? 46 58 ms blank check time 4-byte t bc4 ??78??50 s 1-kbyte t bc1k ? ? 1.61 ? ? 0.369 ms erase operation forcible stop time t sed ? ? 33.6 ? ? 25.6 s start-up area switching setting time t sas ? 13.2 549 ? 7.6 445 ms access window time t aws ? 13.2 549 ? 7.6 445 ms rom mode transition wait time 1 t dis 2??2?? s rom mode transition wait time 2 t ms 3??3?? s
r01ds0273ej0100 rev.1.00 page 103 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.12 e2 dataflash characteristics (flash memory for data storage) note 1. the reprogram/erase cycle is the number of erasing for each block. when the reprogram/erase cycle is n times (n = 100000 ), erasing can be performed n times for each block. for instance, when 1-byte programming is performed 1000 times for different addresses in 1-kbyte block and then the entire block is erased, the reprogram/erase cycle is counted as one. however, programming the same address for several times as one erasing is not enabled (overwriting is prohibited). note 2. characteristic when using the flash memory programmer and the self-programming library provided from renesas electronics . note 3. these results are obtai ned from reliability testing. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. note: does not include the time until each operation of the flash me mory is started after instructions are executed by software. note: the lower-limit frequency of fclk is 1 mhz during programmi ng or erasing of the flash memory. when using fclk at below 4 mhz, the frequency can be set to 1 mhz, 2 mhz, or 3 mhz. a non-integer frequency such as 1.5 mhz cannot be set. note: the frequency accuracy of fclk should be 3.5%. table 5.52 e2 dataflash characteristics (1) item symbol min. typ. max. unit conditions reprogramming/erasure cycle* 1 n dpec 100000 1000000 ? times data retention after 10000 times of n dpec t ddrp 20* 2, * 3 ? ? year t a = +85c after 100000 times of n dpec 5* 2, * 3 ? ? year after 1000000 times of n dpec ?1* 2, * 3 ? year t a = +25c table 5.53 e2 dataflash characteristics (2): high-speed operating mode conditions: 2.7 v vcc 5.5 v, 2.7 v avcc0 5.5 v, vss = avss0 = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +105c item symbol fclk = 1 mhz fclk = 32 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 ? 86 761 ? 40.5 374 s erasure time 1-kbyte t de1k ? 17.4 456 ? 6.15 228 ms 8-kbyte t de8k ? 60.4 499 ? 9.3 231 ms blank check time 1-byte t dbc1 ? ? 48 ? ? 15.9 s 1-kbyte t dbc1k ? ? 1.58 ? ? 0.127 s erase operation forcible stop time t dsed ? ? 21.5 ? ? 12.8 s dataflash stop recovery time t dstop 5.0 ? ? 5 ? ? s table 5.54 e2 dataflash characteristics (3): middle-speed operating mode conditions: 1.8 v vcc = avcc0 ? 2.0 v, 2.0 v vcc 5.5 v, 2.0 v avcc0 5.5 v, vss = avss0 = 0 v temperature range for the progr amming/erasure operation: t a = ?40 to +85c item symbol fclk = 1 mhz fclk = 8 mhz unit min. typ. max. min. typ. max. programming time 1-byte t dp1 ? 126 1160 ? 85.4 818 s erasure time 1-kbyte t de1k ? 17.5 457 ? 7.76 259 ms 8-kbyte t de8k ? 60.5 500 ? 4.2 66.9 ms blank check time 1-byte t dbc1 ? ? 78 ? ? 50 s 1-kbyte t dbc1k ? ? 1.61 ? ? 0.369 ms erase operation forcible stop time t dsed ? ? 33.5 ? ? 25.5 s dataflash stop recovery time t dstop 720 ? ? 720 ? ? s
r01ds0273ej0100 rev.1.00 page 104 of 116 oct 30, 2015 rx130 group 5. electrical characteristics 5.13 usage notes 5.13.1 connecting vcl capacitor and bypass capacitors this mcu integrates an internal voltage-down circuit, which is used for lowering the power supply voltage in the internal mcu to adjust automatically to the optimum level. a 4.7- f capacitor needs to be connected between this internal voltage-down power supply (vcl pin) and vss pin. figure 5.62 to figure 5.64 shows how to connect external capacitors. place an external capacitor close to the pins. do not apply th e power supply volta ge to the vcl pin. insert a multilayer ceramic capacitor as a bypass capacitor between each pair of the power supply pins. implement a bypass capacitor to the mcu power supply pins as close as possible. use a recommended value of 0.1 f as the capacitance of the capacitors. for the capacito rs related to crystal oscillation, see section 9, clock generation circuit in the user?s manual: hardware . for the capacitors related to analog modules, also see section 32, 12-bit a/d converter (s12ade) in the user?s manual: hardware . for notes on designing the printed circuit board, see the descriptions of the application note "hardware design guide" (r01an1411ej). the latest version can be do wnloaded from renesas electronics website.
r01ds0273ej0100 rev.1.00 page 105 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.62 connecting capacitors (80 pins) external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 vcc vss vcl vss vcc rx130 group plqp0080kb-b (80-pin lfqpf) (top view) bypass capacitor 0.1 f note. do not apply the power supply voltage to the vcl pin. use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin. a recommended value is shown for the capacitance of the bypass capacitors.
r01ds0273ej0100 rev.1.00 page 106 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.63 connecting capacitors (64 pins) bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 54 55 51 49 50 52 53 56 57 58 59 60 61 63 64 62 rx130 group plqp0064kb-c PLQP0064GA-A (64-pin lqfp) (top view) vss vcc vcl vss vcc note. do not apply the power supply voltage to the vcl pin . use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin . a recommended value is shown for the capacitance of the bypass capacitors .
r01ds0273ej0100 rev.1.00 page 107 of 116 oct 30, 2015 rx130 group 5. electrical characteristics figure 5.64 connecting capacitors (48 pins) bypass capacitor 0.1 f external capacitor for power supply stabilization 4.7 f bypass capacitor 0.1 f note. do not apply the power supply voltage to the vcl pin. use a 4.7-f multilayer ceramic for the vcl pin and place it close to the pin. a recommended value is shown for the capacitance of the bypass capacitors . 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 1 2 3 4 5 6 7 8 9 10 11 12 38 39 37 40 41 42 43 44 45 47 48 46 rx130 group plqp0048kb-b pwqn0048kb-a (48-pin lqfp) (top view) vss vcc vcl vss vcc 18 17 16 15 14 13
r01ds0273ej0100 rev.1.00 page 108 of 116 oct 30, 2015 rx130 group appendix 2. package dimensions appendix 2. package dimensions information on the latest version of the package dimensions or mountings has been displayed in ?packages? on renesas electronics corporation website. figure a 80-pin lfqfp (plqp0080kb-b)
r01ds0273ej0100 rev.1.00 page 109 of 116 oct 30, 2015 rx130 group appendix 2. package dimensions figure b 64-pin lqfp (PLQP0064GA-A) terminal cross section b1 c1 bp c 2. 1. dimensions " *1" and " *2" do not include mold flash. note) dimension "*3" does not include trim offset. *3 11 6 17 32 33 48 49 64 f *1 *2 x index mark d h d e h e e b p z d z e detail f c a a 2 a 1 l l 1 previous code jeita package code renesas code PLQP0064GA-A 64p6u-a/ ? mass[typ.] 0.7g p-lqfp64-14x14-0.80 1.0 0.125 0.35 1.0 1.0 0.20 0.20 0.145 0.09 0.420.370.32 maxnom min dimension in millimeters symbol reference 14.1 14.0 13.9 d 14.1 14.0 13.9 e 1.4 a 2 16.2 16.0 15.8 16.2 16.0 15.8 1.7 a 0.2 0.1 0 0.70.50.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 y s s
r01ds0273ej0100 rev.1.00 page 110 of 116 oct 30, 2015 rx130 group appendix 2. package dimensions figure c 64-pin lqfp (plqp0064kb-c)
r01ds0273ej0100 rev.1.00 page 111 of 116 oct 30, 2015 rx130 group appendix 2. package dimensions figure d 48-pin hwqfn (pwqn0048kb-a) 2012 renesas electronics corporation. all rights reserved. detail of a part s y e lp sx ba b m a d e 36 37 24 25 12 13 1 48 a s b a s d2 e2 exposed die pad item d2 e2 a min nom max 5.45 5.50 exposed die pad variations 5.55 min nom max 5.45 5.50 5.55 jeita package code renesas code previous code mass (typ.) [g] p-hwqfn48-7x7-0.50 pwqn0048kb-a 48pjn-a p48k8-50-5b4-5 0.13 d e a b e lp 0.40 0.50 7.00 7.00 0.75 0.25 referance symbol min nom max dimension in millimeters 0.70 0.18 0.80 0.30 0.30 0.50 x 0.05 6.95 6.95 7.05 7.05 y 0.05
r01ds0273ej0100 rev.1.00 page 112 of 116 oct 30, 2015 rx130 group appendix 2. package dimensions figure e 48-pin lqfp (plqp0048kb-b)
r01ds0273ej0100 rev.1.00 page 113 of 116 oct 30, 2015 rx130 group revision history classifications - items with technical update document number: changes according to the corresponding i ssued technical update - items without technical update documen t number: minor changes that do not re quire technical update to be issued revision history rx130 gr oup user?s manual: datasheet rev. date description classification page summary 1.00 oct 30, 2015 ? first edition, issued revision history
notes for cmos devices (1) voltage application waveform at input pin: waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between vil (max) and vih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between vil (max) and vih (min). (2) handling of unused input pins: unconnected cm os device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an in ternal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to vdd or gnd via a resist or if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) precaution against esd: a strong electric fi eld, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade t he device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequat e. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be gr ounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touc hed with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. (4) status before initialization: power-on does not necessarily define the in itial status of a mos device. immediately after the power source is turn ed on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o setti ngs or contents of registers. a device is not initialized un til the reset signal is received. a re set operation must be executed immediately after power-on for devices with reset functions. (5) power on/off sequence: in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the po wer supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) input of signal during power off state : do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that re sults from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal cu rrent that passes in the device at this time may cause degradation of internal elem ents. input of signals during th e power off state must be judged separately for each device and according to re lated specifications governing the device.
general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/mcu pr oducts from renesas. for detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products. 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. ? the input pins of cmos products are generally in the high-impedance state. in operation with an unused pin in the open-circuit state, extra electromag netic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal be come possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applie d to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset pr ocess is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provid ed for the possible future expansi on of functions. do not access these addresses; the correct operation of ls i is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program ex ecution, wait until the target clock signal has stabilized. ? when the clock signal is gene rated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only re leased after full stabilization of the clock signal. moreover, when switching to a clock signal produc ed with an external resonator (or by an external oscillator) while program ex ecution is in progress, wait until t he target clock signal is stable. 5. differences between products before changing from one product to another, i.e. to a product with a different part number, confirm that the change will not lead to problems. ? the characteristics of an mpu or mcu in the same group but having a different part number may differ in terms of the internal memory capacity, layout pattern, and other factors, which can affect the ranges of electrical characteristics, such as characteristic values, ope rating margins, immunity to noise, and amount of radiated noise. when changing to a product with a different part number, implement a system-evaluation test for the given product.
notice 1. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information incl uded herein. 3. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rig hts of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any paten ts, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti-crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat t o human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you mus t check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have sp ecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desig n. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics produc t, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measu res. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibi lity of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, in cluding without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufactur e, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this do cument, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or other wise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by yo u or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this docu ment or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-own ed subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2801 scott boulevard santa clara, ca 95050-2549, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 9251 yonge street, suite 8309 richmond hill, ontario canada l4c 9t3 tel: +1-905-237-2004 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2015 renesas electronics corporation. all rights reserved. colophon 5.0

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